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XRT73L00A Datasheet(PDF) 5 Page - Exar Corporation |
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XRT73L00A Datasheet(HTML) 5 Page - Exar Corporation |
5 / 53 page áç áç áç áç XRT73L00A E3/DS3/STS-1 LINE INTERFACE UNIT REV. 2.0.1 III Figure 28. The Behavior of the RPOS and RCLK1 Output Signals While the XRT73L00A is Transmitting Single- Rail Data to the Receiving Terminal Equipment ........................................................................... 38 4.0 Diagnostic Features of the XRT73L00A ................................................................... 38 4.1 THE ANALOG LOCAL LOOP-BACK MODE .............................................................................................. 38 Figure 29. The Analog Local Loop-Back in the XRT73L00A .......................................................................... 39 COMMAND REGISTER CR4 (ADDRESS = 0X04) ........................................................................................... 39 4.2 THE DIGITAL LOCAL LOOP-BACK MODE ............................................................................................... 39 Figure 30. The Digital Local Loop-Back path in the XRT73L00A ................................................................... 40 COMMAND REGISTER CR4 (ADDRESS = 0X04) ........................................................................................... 40 4.3 THE REMOTE LOOP-BACK MODE ......................................................................................................... 40 Figure 31. The Remote Loop-Back Path in the XRT73L00A .......................................................................... 41 4.4 TXOFF FEATURES .............................................................................................................................. 41 COMMAND REGISTER CR4 (ADDRESS = 0X04) ........................................................................................... 41 4.5 THE TRANSMIT DRIVE MONITOR FEATURES .......................................................................................... 41 COMMAND REGISTER CR1 (ADDRESS = 0X01) ........................................................................................... 41 Figure 32. The XRT73L00A Employing the Transmit Drive Monitor Features ............................................... 42 Figure 33. Two LIU’s, Each Monitoring the Transmit Output Signal of the Other LIU IC .............................. 43 4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE ....................................................................................... 43 COMMAND REGISTER CR1 (ADDRESS = 0X01) ........................................................................................... 43 5.0 The Microprocessor Serial Interface ........................................................................ 44 5.1 DESCRIPTION OF THE COMMAND REGISTERS ........................................................................................ 44 TABLE 5: ADDRESSES AND BIT FORMATS OF XRT73L00A COMMAND REGISTERS .............................................. 44 DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER ..................................................................... 44 5.1.1 Command Register - CR0 ...................................................................................................... 44 5.1.2 Command Register - CR1 ...................................................................................................... 45 5.1.3 Command Register - CR2 ...................................................................................................... 46 5.1.4 Command Register - CR3 ...................................................................................................... 46 5.1.5 Command Register - CR4 ...................................................................................................... 46 5.2 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. ...................................................................... 47 TABLE 6: LOOP-BACK MODES ........................................................................................................................... 47 Figure 34. Microprocessor Serial Interface Data Structure ............................................................................ 48 ORDERING INFORMATION ............................................................................................................................ 49 PACKAGE DIMENSIONS ................................................................................................. 49 REVISION HISTORY ..................................................................................................................................... 50 |
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