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XRT73L00A Datasheet(PDF) 1 Page - Exar Corporation |
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XRT73L00A Datasheet(HTML) 1 Page - Exar Corporation |
1 / 53 page Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com áç áç áç áç XRT73L00A E3/DS3/STS-1 LINE INTERFACE UNIT AUGUST 2002 REV. 2.0.1 GENERAL DESCRIPTION The XRT73L00A DS3/E3/STS-1 Line Interface Unit is an improved version of the XRT73L00 and consists of a line transmitter and receiver integrated on a single chip and is designed for DS3, E3 or SONET STS-1 applications. XRT73L00A can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) rates. In the transmit direction, the XRT73L00A encodes in- put data to either B3ZS (for DS3/STS-1 applications) or HDB3 (for E3 applications) format and converts the data into the appropriate pulse shapes for transmis- sion over coaxial cable via a 1:1 transformer. In the receive direction the XRT73L00A performs equalization on incoming signals, performs Clock Re- covery, decodes data from either B3ZS or HDB3 for- mat, converts the receive data into TTL/CMOS for- mat, checks for LOS or LOL conditions and detects and declares the occurrence of line code violations. The XRT73L00A also contains a 4-Wire Microproces- sor Serial Interface for accessing the on-chip Com- mand registers. FEATURES • Incorporates an improved Timing Recovery circuit and is pin and functional compatible to XRT73L00 • Meets E3/DS3/STS-1 Jitter Tolerance Require- ments • Full Loop-Back Capability • Transmit and Receive Power Down Modes • Full Redundancy Support • Contains a 4-Wire Microprocessor Serial Interface • Uses Minimum External components • Single +3.3V Power Supply • 5 V Tolerant pins • -40°C to +85°C Operating Temperature Range • Available in a 44 pin TQFP package APPLICATIONS • Interfaces to E3, DS3 or SONET STS-1 Networks • CSU/DSU Equipment • PCM Test Equipment • Fiber Optic Terminals • Multiplexers FIGURE 1. BLOCK DIAGRAM OF THE XRT73L00A AG C / E qualizer Se ria l P rocesso r In te rfa ce P eak De te ctor LO S D e te ctor S lice r Clo ck R e covery Da ta R e covery In ve rt Loop M U X HDB 3 / B3 Z S D e code r LO S T H R SD I SD O /(L C V ) SC lk CS R E G R ESET RT IP RRIN G RE Q D IS D e vice M onito r MT IP MR IN G DM O Tra n sm it Logic Du ty Cycle A d ju st TTIP TR IN G Pu lse S haping HDB 3 / B3 Z S E n coder E 3 S T S -1 /DS 3 H o s t/(H W ) RL O L E X C L K IC T RCL KINV Tx C ontro l DR/S R RL O S LLB RL B E N D E CDIS TA O S TP D A TA TN D A TA TC lk TX LE V TX O F F RCL K1 RNE G RP O S L C V /(RCL K2) |
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