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XRT73L00A Datasheet(PDF) 10 Page - Exar Corporation |
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XRT73L00A Datasheet(HTML) 10 Page - Exar Corporation |
10 / 53 page XRT73L00A áç áç áç áç E3/DS3/STS-1 LINE INTERFACE UNIT REV. 2.0.1 7 22 CS/(DR/SR)I Microprocessor Serial Interface - Chip Select/Encoder and Decoder Dis- able The function of this input pin depends upon whether the XRT73L00A is operat- ing in the HOST or the Hardware Mode. HOST Mode - Chip Select Input: The Local Microprocessor must assert this pin (e.g., set it to “0”) in order to enable communication with the XRT73L00A via the Microprocessor Serial Inter- face. Hardware Mode - Dual-Rail/Single-Rail Select Input: Setting this input pin “High” configures the XRT73L00A to operate in the Dual- Rail Mode. When the XRT73L00A is operating in this mode, then the Receive Section of the LIU IC outputs the Recovered Data via both RPOS and RNEG output pins. Setting this input pin “Low” configures the XRT73L00A to operate in the Single- Rail Mode. When the XRT73L00A is operating in this mode, the Receive Sec- tion of the LIU IC outputs the Recovered Data via the RPOS output pin in a binary data stream. No data will output via the RNEG output pin. 23 RLOL O Receive Loss of Lock Output Indicator This output pin toggles “High” if the XRT73L00A has detected a Loss of Lock Condition. The XRT73L00A declares an LOL (Loss of Lock) Condition if the recovered clock frequency deviates from the Reference Clock frequency (avail- able at the EXCLK input pin) by more than 0.5%. NOTE: The RCLK1/2 output pins are sourced by the signal applied at the EXCLK input pin anytime the XRT73L00A declares an LOL condition. 24 RLOS O Receive Loss of Signal Output Indicator This output pin toggles “High” if the XRT73L00A has detected a Loss of Signal Condition in the incoming line signal. The criteria the XRT73L00A uses to declare an LOS Condition depends upon whether the device is operating in the E3 or DS3/STS-1 Mode. 25 DGND **** Digital Ground 26 DVDD **** Digital Power Supply 27 EXCLK I External Reference Clock Input: Apply a line-rate clock signal to this input pin. This signal is a 34.368MHz clock signal for E3 applications, a 44.736 MHz clock signal for DS3 applications or a 51.84 MHz clock signal for SONET STS-1 applications. NOTE: This input pin functions as the source of the RxCLK output clock signal any time the XRT73L00A declares an LOL condition. 28 RxDGND **** Receiver Digital Ground 29 RxDVDD **** Receiver Digital Power Supply PIN DESCRIPTION PIN #SYMBOL TYPE DESCRIPTION |
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