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P87CL52X2BDH Datasheet(PDF) 6 Page - NXP Semiconductors |
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P87CL52X2BDH Datasheet(HTML) 6 Page - NXP Semiconductors |
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6 / 47 page  Philips Semiconductors Product data P87CL52X2/54X2 80C51 8-bit microcontroller family 8K/16K OTP 256 bytes RAM ROMless low voltage (1.8 V to 3.3 V), low power, high speed (33 MHz) 2003 May 14 6 PIN DESCRIPTIONS PIN NUMBER MNEMONIC LQFP TSSOP TYPE NAME AND FUNCTION VSS 16 9 I Ground: 0 V reference. VCC 38 29 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 37–30 28–21 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port with Schmitt trigger inputs. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. P1.0–P1.7 40–44, 1–3 30–37 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger inputs. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Alternate functions for Port 1 include: 40 30 I/O T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out) 41 31 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control P2.0–P2.7 18–25 10–17 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger inputs. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. P3.0–P3.7 5, 7–13 1–6 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger inputs. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: 5 1 I RxD (P3.0): Serial input port 7 2 O TxD (P3.1): Serial output port 8 I INT0 (P3.2): External interrupt1 9 3 I INT1 (P3.3): External interrupt 10 4 I T0 (P3.4): Timer 0 external input 11 I T1 (P3.5): Timer 1 external input1 12 5 O WR (P3.6): External data memory write strobe 13 6 O RD (P3.7): External data memory read strobe RST 4 38 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. ALE 27 19 O Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. PSEN 26 18 O Program Store Enable: The read strobe to external program memory. When the P87CL5xX2 is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA/VPP 29 20 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to 0FFFH. XTAL1 15 8 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 14 7 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5 V or VSS – 0.5 V, respectively. 1. Absent in the TSSOP38 package. |
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