Philips Semiconductors

Product data

PCK2022RA

CK00 (100/133 MHz) spread spectrum differential

system clock generator

2003 Jul 31

3

PIN DESCRIPTION

PIN(S)

SYMBOL

FUNCTION

1

IOCLK

Dual frequency pin which can operate at either 33 MHz or 66 MHz per the selection table.

3, 4

48M_0/SELA

48M_1/SELB

3.3 V fixed 48 MHz clock outputs. During power-up pins function as latched inputs that enable SELA and

SELB prior to the pins being used for output of 3 V at 48 MHz. Part must be clocked to latch data in.

7, 8

HCLK0

HCLKB0

Host output pair 0

10, 11

HCLK1

HCLKB1

Host output pair 1

13, 14

HCLK2

HCLKB2

Host output pair 2

16, 17

HCLK3

HCLKB3

Host output pair 3

42, 21

HCLK4

HCLKB4

Host output pair 4

39, 38

HCLK5

HCLKB5

Host output pair 5

36, 35

HCLK6

HCLKB6

Host output pair 6

33, 32

HCLK7

HCLKB7

Host output pair 7

19

REFCLK/SELC

3.3 V fixed 14.318 MHz output. During power-up, pin functions as a latched input that enables SELC prior

to the pin being used for the clock output. Part must be clocked to latch data in.

20

SPREAD

Enables spread spectrum mode when held LOW on differential host outputs and 33 MHz IOCLK clocks.

Asserts LOW.

21

XIN

Crystal input

22

XOUT

Crystal output

26

This pin controls the reference current for the host pairs. This pin requires a fixed precision resistor tied to

ground in order to establish the correct current.

29, 30

MULTSEL0

MULTSEL1

Select input pin used to control the scaling of the HCLK and HCLKB output current.

44

PWRDWN

Device enters power-down mode when held LOW. Asserts LOW.

48

SEL100/133

Select input pin for enabling 133 MHz or 100 MHz CPU outputs

2, 6, 12,

18, 24, 31,

37, 43

3.3 V power supply

5, 9, 15,

21, 28, 34,

40, 47

GND

Ground

25, 46

3.3 V power supply for analog circuits

27, 45

AGND

Ground for analog circuits