Philips Semiconductors

Product data

SA57026

300 mA LDO with ON/OFF control and

independent delayed RESET function

2003 Oct 13

5

APPLICATION INFORMATION

Input capacitor

An input capacitor of

≥1 µF is required to eliminate the AC coupling

GND pin (not more than 1 cm) and returned to a clean analog

ground. Any good quality ceramic, tantalum or film capacitor will

work.

Output capacitor

Phase compensation is made for securing stable operation, even if

the load current varies. For this reason, an output capacitor with

good frequency characteristics is needed. Set it as close to the

circuit as possible, with wires as short as possible.

Tha value of the output capacitance has to be at least 47

µF

than batteries, supply-noise rejection and transient response can be

improved by increasing the value of the input and output capacitors

and employing passive filtering techniques.

ON/OFF

The regulator is fully enabled when a logic HIGH is applied to this

input. The regulator enters shutdown when a logic LOW is appplied

to this input. During shutdown, regulator output voltage falls to zero,

RESET remains valid and supply current is reduced to 5

µA (typ). If

RESET output

The SA57066 has an Active-LOW RESET output. The RESET

output is driven Active-LOW within 30

µs typical (when Cd is zero

capacitance). The time delay can be adjusted up to 10 ms typical

(when Cd is 0.1

thre reset threshold.

RESET output delay operation with an external capacitor from

Cd pin to GND

pin voltage starts to increase (charges up the external capacitor).

While the RESET output remains at LOW state condition until the

typical; after that, the RESET output is reversed to HIGH state

condition.

Cd of an external cpacitor as shown in Equation (1):

t

6

C

Eqn. (1)

(Time is expressed in seconds; capacitance in Farads.)

PCB layout

The component placement around the LDO should be done carefully

to achieve good dynamic line and load response. The input and

noise capacitors should be kept close to the LDO.

The rise in junction temperature depends on how efficiently the heat

is carried away from the junction to ambient. The junction to lead

thermal impedance is a characteristic of the package and fixed. The

thermal impedance between lead to ambient can be reduced by

increasing the copper area on the PCB. Increase the input, output

and ground trace area to reduce the junction-to-ambient impedance.

SA57026

5

7

2

4

6

1

3

Cd

C

0.1

µF

47

µF

R

ON/OFF

R

4.7 k

Ω

RESET

C

1

µF

SL01530

Figure 3. Typical application circuit.