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LP2995MRX Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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LP2995MRX Datasheet(HTML) 3 Page - National Semiconductor (TI) |
3 / 13 page Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. PVIN, AVIN, VDDQ to GND −0.3V to +6V Storage Temp. Range −65˚C to +150˚C Junction Temperature 150˚C SO-8 Thermal Resistance ( θ JA) 151˚C/W LLP-16 Thermal Resistance ( θ JA) 51˚C/W Lead Temperature (Soldering, 10 sec) 260˚C ESD Rating (Note 7) 1kV Operating Range Junction Temp. Range (Note 5) 0˚C to +125˚C AVIN to GND 2.2V to 5.5V PVIN to GND 2.2V to AVIN Electrical Characteristics Specifications with standard typeface are for T J = 25˚C and limits in boldface type apply over the full Operating Temperature Range (T J = 0˚C to +125˚C). Unless otherwise specified, AVIN = PVIN = 2.5V, VDDQ = 2.5V (Note 6). Symbol Parameter Conditions Min Typ Max Units V REF V REF Voltage I REF_OUT = 0mA 1.21 1.235 1.26 V VOS VTT V TT Output Voltage Offset I OUT =0A (Note 2) −15 −20 015 20 mV ∆V TT/VTT Load Regulation (Note 3) I OUT = 0 to 1.5A 0.5 % I OUT = 0 to −1.5A −0.5 Z VREF V REF Output Impedance I REF = −5µA to +5µA 5 k Ω Z VDDQ VDDQ Input Impedance 100 k Ω I q Quiescent Current I OUT =0A (Note 4) 250 400 µA Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: VTT offset is the voltage measurement defined as VTT subtracted from VREF. Note 3: Load regulation is tested by using a 10ms current pulse and measuring VTT. Note 4: Quiescent current defined as the current flow into AVIN. Note 5: At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at θJA = 151˚ C/W junction to ambient with no heat sink. The device in the LLP-16 must be derated at θJA = 51˚ C/W junction to ambient. Note 6: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 7: The human body model is a 100pF capacitor discharged through a 1.5k Ω resistor into each pin. www.national.com 3 |
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