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DA14580-01AT1 Datasheet(PDF) 5 Page - Dialog Semiconductor |
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DA14580-01AT1 Datasheet(HTML) 5 Page - Dialog Semiconductor |
5 / 155 page Datasheet Revision 3.4 09-Nov-2016 CFR0011-120-01 5 of 155 © 2014 Dialog Semiconductor DA14580 Bluetooth Low Energy 4.2 SoC FINAL Figure 4: QFN40 Pin Assignment Table 1: Pin Description Pin Name Type Drive (mA) Reset State Description General Purpose I/Os P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 DIO DIO DIO DIO DIO DIO DIO DIO 4.8 I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. P1_0 P1_1 P1_2 P1_3 P1_4/SWCLK P1_5/SW_DIO DIO DIO DIO DIO DIO DIO 4.8 I-PD I-PD I-PD I-PD I-PD I-PU INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. This signal is the JTAG clock by default This signal is the JTAG data I/O by default P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7 P2_8 P2_9 DIO DIO DIO DIO DIO DIO DIO DIO DIO DIO 4.8 I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. NOTE: This port is only available on the QFN40/QFN48 pack- ages. 8 7 6 5 4 3 2 1 23 24 25 26 27 28 29 30 Pin 0: GND plane P0_0 P0_1 P0_2 P0_3 NC P0_4 P2_1 XTAL16Mm XTAL16Mp P1_3 P1_2 SW_CLK SWDIO P1_1 VBAT1V 10 9 P0_7 21 22 SWITCH P1_0 DA14580 (Top View) P0_5 P0_6 |
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