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M6313LGVCN Datasheet(PDF) 2 Page - MTRONPTI |
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M6313LGVCN Datasheet(HTML) 2 Page - MTRONPTI |
2 / 3 page MtronPTI reserves the right to make changes to the product(s) and service(s) described herein without notice. No liability is assumed as a result of their use or application. Please see www.mtronpti.com for our complete offering and detailed datasheets. Contact us for your application specific requirements: MtronPTI 1-800-762-8800. M630x Series 5x7 mm, 3.3/2.5/1.8 Volt, LVPECL/LVDS/CML/CMOS, TCXO/TCVCXO Parameter Symbol Min. Typ. Max. Units Conditions/Notes Frequency Range FR 50 1400 MHz LVPECL, LVDS, CML (See Note 1) 50 135 MHz CMOS Initial Accuracy FI -1 +1 ppm @ +25 °C Frequency Stability ∆ FT/F ppm (Fmax - Fmin)/2 (See Note 2) Frequency Vs. Aging ∆ FTIME/F -3 +3 ppm First year -1 +1 ppm Thereafter (per year) Frequency Vs. Supply Voltage ∆ FVDD/F ±0.40 ppm 5% voltage variation Frequency Vs. Reflow ±0.75 ppm 2 reflows max. Frequency Vs. Load ∆ FLOAD/F ±0.20 ppm 5% supply voltage variation Operating Temperature TA °C Storage Temperature TSTG -55 +125 °C Operating Voltage VCC/VS/VDD 3.135 3.3 3.465 V M6300 2.375 2.5 2.625 V M6301 1.71 1.8 1.89 V M6302 Operating Current ICC 125 mA LVPECL 100 mA LVDS 110 mA CML 90 mA CMOS Rise/Fall Time tR/tF 0.35 ns LVPECL, LVDS, CML 6 ns CMOS Logic “1” Level VOH VCC - 1.02 V LVPECL 90 % VDD CMOS Logic “0” Level VOL VCC - 1.63 V LVPECL 10 % VDD CMOS Common Mode Output Voltage VCM 1.2 V LVDS Symmetry (Duty Cycle) tDC 45 55 % @ 50% VDD (CMOS) 45 55 % @ 50% of waveform (LVPECL) 45 55 % @ 1.25 V (LVDS) Output Voltage Level 0.7 0.95 1.2 Vpk-pk CML Tuning Range ±5 ppm VCTCXO only (See Note 3) Voltage Control Range VC 0.18 0.90 1.62 V @ 1.8 V supply (VCTCXO only - Pad 2) 0.25 1.25 2.25 V @ 2.5 V supply (VCTCXO only - Pad 2) 0.30 1.65 3.00 V @ 3.3 V supply (VCTCXO only - Pad 2) Output Skew 20 ps LVPECL 15 ps CML 20 ps LVDS Output Load LVPECL (See Note 4) LVDS, CML (See Note 4) CMOS (See Note 4) Enable/Disable Function 80 % Output Enabled (Option B or G) 0.5 V Output Disabled Enable/Disable Function 0.5 V Output Enabled (Option S or M) 80 % Output Disabled Phase Noise (Typical) 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz Offset from carrier @ 622.080 MHz (LVPECL) -60 -90 -120 -127 -133 dBc/Hz @ 100.000 MHz (HCMOS) -70 -103 -123 -131 -136 dBc/Hz @ 50.000 MHZ (HCMOS) -77 -109 -129 -137 -141 dBc/Hz Shock Vibration Solderability Hermeticity Thermal Shock Thermal Cycle Note 4: Refer to the load circuit diagram in this data sheet. 1 X 10-8 atm cc/sec of helium (Crystal only) Per MIL-STD-883, Method 1011, Condition A Per MIL-STD-883, Method 1010, Condition B Per MIL-STD-202, Methods 201 & 204 Per EIAJ-STD-002 Per MIL-STD-202, Method 213, Condition C See Ordering Information Note 1: Contact factory for frequencies over 945 MHz. Note 2: Contact factory for less than ±1 ppm frequency stability. Note 3: Contact factory for other tuning range options. VDC 100 Ω Differential 15 pF See Ordering Information 50 Ω to (VCC - 2) |
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