10

T6818/T6828

4530C–BCD–11/03

4.16

Low-side output switch

off delay

(1)

V

t

doff

3µs

A

4.17

Dead time between

corresponding high-

and low-side switches

R

t

1

µs

A

5

Logic Inputs DI, CLK, CS, INH

5.1

Input voltage low-level

threshold

4-6, 10

V

IL

0.3

´

V

VCC

V

A

5.2

Input voltage high-level

threshold

4-6, 10

0.7

´

V

VCC

V

A

5.3

Hysteresis of input

voltage

4-6, 10

DV

I

50

700

mV

B

5.4

Pull-down current pin

DI, CLK, INH

V

5, 6, 10

I

PD

10

65

µA

A

5.5

Pull-up current

Pin CS

4

-65

-10

µA

A

6

Serial Interface – Logic Output DO

6.1

Output-voltage low level I

9

V

DOL

0.4

V

A

6.2

Output-voltage high

level

I

9

V

DOH

V

0.7 V

V

A

6.3

Leakage current

(tristate)

V

0V < V

9

I

DO

-10

10

µA

A

7

Inhibit Input - Timing

7.1

Delay time from

standby to normal

operation

t

dINH

100

µs

A

Electrical Characteristics (Continued)

7.5 V < V

No.

Parameters

Test Conditions

Pin

Symbol

Min.

Typ.

Max.

Unit

Type*

*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of final

level. Device not in standby for t > 1 ms