FEDL9213-01

1Semiconductor

ML9213

5/19

PIN DESCRIPTIONS

Pin

Symbol

ML9213GA ML9213GP

Type

Description

V

DISP

65, 80

63, 78

—

Power supply pins for VFD driver circuit.

These should be connected externally.

V

DD

25

23

—

Power supply pin for logic drive.

D-GND

24, 40

22, 38

—

L-GND

33

31

—

D-GND is ground pin for the VFD driver circuit. L-GND is ground

pin for the logic circuit. These should be connected externally.

SEG1 to 37

42 to 64,

66 to 79

40 to 62,

64 to 77

O

Segment (anode) signal output pins for a VFD tube. These pins

can be directly connected to the VFD tube. External circuit is not

required.

I

SEG38 to 56

1 to 19

79, 80,

1 to 17

O

Segment (anode) signal output pins for a VFD tube. These pins

can be directly connected to the VFD tube. External circuit is not

required.

I

GRID1

20

18

GRID2

21

19

GRID3

22

20

O

Inverted Grid signal output pins. Since these pins are connected

to the pre-driver, an external circuit is required.

I

CS

29

27

I

Chip select input pin.

Data is not transferred when CS is set to a Low level.

CLOCK

30

28

I

Shift clock input pin.

Serial data shifts at the rising edge of the CLOCK.

DATA IN

31

29

I

Serial data input pin (positive logic). Data is input to the shift

register at the rising edge of the CLOCK signal.

DUP/

TRI

35

33

I

Duplex/Triplex operation select input pin.

Duplex (1/2 duty) operation is selected when this pin is set to V

Triplex (1/3 duty) operation is selected when this pin is set to L-

GND.

M/

S

36

34

I

Master/Slave mode select input pin.

Master mode is selected when this pin is set to V

Slave mode is selected when this pin is set to L-GND.

DIM IN

26

24

I

Dimming pulse input.

When the slave mode is selected, connect this pin to the master

side DIM OUT pin. The pulse width of all the segment outputs is

controlled by an input pulse width of DIM IN. When the master

mode is selected, input to this pin is ignored; therefore, connect

this pin to V

outputs is controlled by the built-in digital dimming circuit, and the

pulse width of all the grid outputs is controlled by the internal

timing generator.

SYNC IN1

27

25

SYNC IN2

28

26

I

Synchronous signal input.

When the slave mode is selected, connect these pins to the

master side SYN COUT1 and 2 pins.

When the master mode is selected, input to these pins is ignored;

therefore, connect these pins to V

DIM OUT

39

37

O

Dimming pulse output.

Connect this pin to the slave side DIM IN pin.