FEDL9460-01

LAPIS Semiconductor

ML9460

6/27

4. Functional Description

4.1

Internal Blocks

4.1.1 Liquid Crystal Drive Circuit

The liquid crystal drive circuit outputs three levels for liquid crystal drive.

One of the three liquid crystal drive

levels (V2, MV2, VC) is selected and output according to the combination of data stored n the shift register

circuit and FR, as shown below.

FR

Display data

DSPOF

Output level

*

*

"L"

VC

"L"

"L"

"H"

VC

"L"

"H"

"H"

V2

"H"

"L"

"H"

VC

"H"

"H"

"H"

MV2

*: Don't care

The number of output pins is set by the SEL1 and SEL2 settings, as shown below.

SEL1

SEL2

Number of output pins

"H"

"H"

240 outputs (O1, O2, O3,

, O239, O240)

"H"

"L"

200 outputs (O21, O22, O23,

, O219, O220)

"L"

"H"

160 outputs (O41, O42, O43,

, O199, O200)

"L"

"L"

120 outputs (O61, O62, O63,

, O179, O180)

Pins that are made disabled by the SEL1 and SEL2 pins will output the nonselective level signal (VC)

synchronized with the FR signal.

4.1.2 Level Shifter

The level shifter converts 5 V signals to high-voltage signals used for liquid crystal drive by multiplying the

voltage.

4.1.3 Bidirectional Shift Register

The device is equipped with a 240-bit bidirectional shift register, where the first line signals that are input from

the DIO1 and DIO2 pins are shifted sequentially.

The shift direction is deterrmined by the SHL pin setting.

Relationship between SHL, DIO1, and DIO2

SHL

DIO1

DIO2

"H"

Serial output

Serial input

"L"

Serial input

Serial output