FEDL9488-01 datasheet(11/31 Pages) LAPIS

Part #	FEDL9488-01

Description	Static, 1/2 Duty, 1/3 Duty, 1/4 Duty 80 Outputs LCD Driver

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Manufacturer	LAPIS [LAPIS Semiconductor Co., Ltd.]

Direct Link	http://www.lapis-semi.com/

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11 / 31 page

FEDL9488-01

ML9488

11/31

60-63

SYNCB

I/O

Input/output pin for common synchronization.

It has a schmitt circuit.

It becomes the synchronization signal output pin in the master mode (M/S

pin = "H").

It becomes the synchronization signal input pin in the slave mode (M/S pin = "L").

For cascade connection, connect all of the involved ML9488s' SYNC pins by

the common line.

65-66

I2C

I

Interface switching pin.

It has a schmitt circuit.

When this pin is "H", the interface is I

2C.

When this pin is "L", the interface is three-wire serial.

20-21

DATA

(SDA)

I

Display data input pin. It has a schmitt circuit.

I2C="L": Serial interface; DATA

Input the display data in the order of SEG80, SEG79, ... , SEG2, and SEG1.

The display data turns on at "H" and turns off at "L".

I2C="H": I

2C interface; SDA

Input the display data in units of 8 bits.

The display data turns on at "H" and

turns off at "L".

This pin has a built-in noise filter through which noises in widths up to 50 ns

are removed.

This noise filter is valid only when I2C = "H".

22-23

CLOCK

(SCL)

I

Shift clock input pin for display data. It has a schmitt circuit.

I2C="L": Serial interface; CLOCK

The display data input to the DATA pin is serially input to the shift register at

the CLOCK signal rise.

I2C="H": I

2C interface; SCL

The display data input to the SDA pin is serially input to the shift register at

the SCL signal rise.

This pin has a built-in noise filter through which noises in widths up to 50 ns

are removed.

This noise filter is valid only when I2C = "H".

24-25

LOAD

I

Input pin for the load signal of display data.

It has a schmitt circuit.

I2C="L": Serial interface; LOAD

The display data in the shift register is transmitted as is to the segment driver

for the "H" duration. When this pin is brought into "L", the shift register is

disconnected from the segment driver. The display data in the shift register

immediately before it become "L" is held in the data latch and transmitted to

the segment driver.

I2C="H": I

2C interface

Use this pin as it is connected to GND.

17-19

SDAACK

O

I2C="L": Serial interface

Use this pin as it is opened.

I2C="H": I

2C interface

The I

2C bus acknowledge output signal. Normally, use it as it is connected

with the SDA pin.

Connect an external pull-up resistor whenever

necessary, as it is an open drain pin.

The pull-up connection destination

supply voltage shall be the VDD supply voltage or less.

69-70

POCEB

I

Internal POC circuit enable pin.

It has a schmitt circuit.

When this pin is "H", the POC circuit becomes OFF and the constant current

(8µA) is cut.

The RESETB pin pull-up resistor is cut as well.

When this pin is "L", the POC circuit becomes ON.

The RESETB pin is connected to a pull-up resistor.

44-45

RESETB

*3

I

Reset signal input pin for initializing inside the IC.

It has a schmitt circuit.

The "L" level enables the reset. This pin has an Internal pull-up resistor.

When POCEB = "H", input the external reset signal to this pin.

When POCEB = "L", the power-on reset operation is available by open this

pin.

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FEDL9488-01 Datasheet(PDF) 11 Page - LAPIS Semiconductor Co., Ltd.

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