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FEDL610406-03 Datasheet(PDF) 5 Page - LAPIS Semiconductor Co., Ltd. |
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FEDL610406-03 Datasheet(HTML) 5 Page - LAPIS Semiconductor Co., Ltd. |
5 / 30 page FEDL610406-05 ML610404/ML610405/ML610406 5/30 BLOCK DIAGRAM Block Diagram of ML610404/ML610405/ML610406 * Secondary function or Tertiary function “*1”: Select among 21 segments x 5 commons, 22 segments x 4 commons, 23 segments x 3 commons, and 24 segments x 2 commons with the register “*2”: Select among 25 segments x 5 commons, 26 segments x 4 commons, 27 segments x 3 commons, and 28 segments x 2 commons with the register “*3”: Select among 29 segments x 5 commons, 30 segments x 4 commons, 31 segments x 3 commons, and 32 segments x 2 commons with the register Figure 1 Block Diagram of ML610404/ML610405/ML610406 Program Memory (ROM) 8Kbyte RAM 256byte Interrupt Controller CPU (nX-U8/100) Timing Controller EA SP Instruction Decoder BUS Controller Instruction Register TBC INT 4 INT 1 WDT INT 4 8bit Timer × 4 Capture × 2 GPIO INT 6 Data-bus Melody INT 1 MD0* TEST0 RESET_N OSC XT0** XT1** LSCLK* OUTCLK* Power VDDL LCD Driver COM0 to COM4 (*1)(*2)(*3) SEG0 to SEG23 (ML610404) (*1) SEG0 to SEG27 (ML610405) (*2) SEG0 to SEG31 (ML610406) (*3) LCD BIAS VL1, VL2, VL3 C1, C2 RC-ADC × 2 CS0* IN0* RS0* RT0* RCT0* RCM* CS1* IN1* RS1* RT1* RESET & TEST ALU EPSW1~3 PSW ELR1~3 LR ECSR1~3 DSR/CSR PC GREG 0~15 VDD VSS INT 1 Display register 320bit Display Allocation RAM P00 to P04 P20 to P23, P24 P30 to P35 P40 to P47 P50 to P57 P60 to P67 (ML610404) P60 to P63 (ML610405) SSIO × 2 SCK0* SIN0* SOUT0* INT 2 SCK1* SIN1* SOUT1* UART RXD0* TXD0* INT 1 INT 1 PWM PWM0* |
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