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TMS4C2972-26DT Datasheet(PDF) 10 Page - Texas Instruments |
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TMS4C2972-26DT Datasheet(HTML) 10 Page - Texas Instruments |
10 / 26 page TMS4C2972 245760 BY 12-BIT FIELD MEMORY SMGS671 – OCTOBER 1997 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 reset read (RSTR) (continued) On the first four positive SRCK transitions after RSTR has gone high, the data states of OE and RE are checked to determine whether the read pointer is to be set to the beginning of any one of its 6 144 blocks or if the pointer is to be set to 0 (see Figure 2). To set the read pointer to an address other than 0, the following four conditions all have to be met: 1. On first positive SRCK transition: OE must be low and RE must be high. 2. On second positive SRCK transition: OE must be low and RE must be high. 3. On third positive SRCK transition: OE must be high and RE must be low. 4. On fourth positive SRCK transition: OE must be high and RE must be low. If any one of these conditions is not met, the memory operates exactly like a TMS4C2970 until the next positive RSTR transition. On the first and second positive SRCK transitions, the memory operates exactly like a TMS4C2970, regarding its response to the control signals OE and RE. Once all the above conditions are met, the outputs will remain disabled regardless of the state of OE. If all four check conditions above have been met, OE no longer controls the state of the outputs and it can be used to set the read pointer to a new block address. This is done by clocking in the data states of the OE pin during the next 13 positive SRCK transitions. The MSB of this address is clocked in on the 5th positive SRCK transition, the LSB on the 17th transition. Only block values between 0 and 6143 are recognized. The user must avoid clocking in a value above 6143 because this may result in improper device operation or lock-up. Recovery from this lock-up will require a TMS4C2970-like reset operation to be performed. After a block address has been clocked in, RE and OE must be kept low for at least another 55 SRCK clock cycles to satisfy the read latency requirements of the memory. After that, sequential addressing may start at the beginning of the new block by bringing RE and OE high. During the entire control sequence to change the read pointer, only one positive RSTR transition is allowed. After RSTR has been kept high during the first positive SRCK transition, it can be maintained high or brought low as desired. But once RSTR has gone low, it cannot be brought high again until the read latency is satisfied. Bringing RSTR high earlier may cause improper operation of the device. RSTR can be kept high for many cycles, the essential actions detailed above are initiated by the first or the second SRCK cycle, if reset to zero is desired, or during the following 70 SRCK cycles. After RSTR is brought low, it must remain low for at least two active SRCK cycles (that is, while RE is high) , before another reset read operation can take place. data outputs (Q0 – Q11) and serial-read clock (SRCK) Data outputs are determined by the state of RE and OE at the rising edge of SRCK. If the outputs change state because the read pointer was advanced, they remain in the previous state for at least the output hold time interval th(OUT) and assume the new valid state after the access time interval tAC. See the timing diagrams for details. The three-state output buffer provides direct TTL compatibility and no pull-up resistors are required. Data output has the same polarity as data input. read enable (RE) RE is used to enable or disable incrementing the internal read address pointer. When the RE input is at logic high, rising edges of the SRCK will increment the pointer. When the RE input is at logic low, the pointer will not be incremented. RE setup and hold times are referenced to the rising edge of SRCK. |
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