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TMS320VC5501 Datasheet(PDF) 3 Page - Texas Instruments |
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TMS320VC5501 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 193 page  Revision History 3 December 2002 − Revised November 2004 SPRS206H REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPRS206G device-specific data sheet to make it an SPRS206H revision. Scope: Deleted Section 7.1 (Ball Grid Array Mechanical Data) and Section 7.2 (Low-Profile Quad Flatpack Me- chanical Data). Mechanical drawings of the 201-terminal GZZ, 201-terminal ZZZ, and 176-pin PGF packages will be appended to this document via an automated process. Added 201-terminal ZZZ package information/data, added Section 4.1 [Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability], added Section 6.2 (Packaging Information), etc. PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS Global: − added 201-terminal ZZZ package information/data − updated title of SPRU146 to “TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module Reference Guide” − updated title of SPRU592 to “TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide” − moved “Package Thermal Resistance Characteristics” section to Section 6, Mechanical Data 15 Section 1, TMS320VC5501 Features: − added 201-terminal ZZZ package to “Packages” feature 17 Section 2.2.1: − changed title from “Ball Grid Array (GZZ)” to “Ball Grid Array (GZZ and ZZZ)” − updated “The TMS320VC5501 is offered in ...” paragraph 17 Figure 2−1: − changed title from “201-Terminal GZZ Ball Grid Array (Bottom View)” to “201-Terminal GZZ and ZZZ Ball Grid Array (Bottom View)” 17 Table 2−1: − changed title from “201-Terminal GZZ Ball Grid Array Thermal Ball Locations” to “201-Terminal GZZ and ZZZ Ball Grid Array Thermal Ball Locations” 18 Table 2−2: − changed title from “201-Terminal GZZ Ball Grid Array Ball Assignments” to “201-Terminal GZZ and ZZZ Ball Grid Array Ball Assignments” 21 Table 2−4, Signal Descriptions: − updated Function column of HCS, HDS1, HDS2, and HPIENA 41 Figure 3−2, TMS320VC5501 Memory Map: − added “Byte Address” above addresses − added footnote about CE space size 57 Updated Section 3.7, Host-Port Interface (HPI) 76 Section 3.9.6, Reset Sequence: − updated “After all internal delay cycles have expired ...” bulleted item 113 Table 3−56, Peripheral Bus Controller Configuration Registers: − added Time-Out Control Register (TOCR) at 0x9000 132 Section 4: − renamed section from “Documentation Support” to “Support” |
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