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ADC700RH Datasheet(PDF) 5 Page - Burr-Brown (TI) |
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ADC700RH Datasheet(HTML) 5 Page - Burr-Brown (TI) |
5 / 12 page 5 ® ADC700 PIN CONFIGURATION DESCRIPTION AND OPERATING FEATURES The ADC700 is a 16-bit resolution successive approxima- tion A/D converter. Parallel digital data as well as serial data is available. Several features have been included in the ADC700 making it easier to interface with microprocessors and/or serial data systems. Several analog input ranges are available. Some of the key operating features are described here. More detail is given in later sections of the data sheet. Refer to the block diagram above. RESET The ADC700 has a Reset input that must be asserted upon power-up or after a power interruption. This initializes the SAR, the output buffer register and Data Ready flag. Since microprocessor systems already use a power-on reset circuit, the same system reset signal can be used to initialize the ADC700. PARALLEL DATA The parallel data output is available through an 8-bit port with 3-state output drivers. High byte and low byte are selected by HBEN (pin 10). A buffer/latch is included between the successive approxi- mation register (SAR) and the 3-state drivers. This feature permits more flexible interface timing than is possible from most successive approximation converters. The “old” word can be read during the next conversion. A Data Ready flag (pin 12) is asserted when a “new” word is in the buffer register. The Data Ready flag goes low (“0”) when the most significant byte (high byte) is read. If the “old” word is not read, or if only the least significant byte (low byte) is read, Data Ready is not reset. The next conversion output will overwrite the data latch when the conversion is complete. The Data Ready flag remains high. Refer to timing diagrams in the Specifications section. SERIAL DATA Sixteen-bit serial data output is available (pin 11) along with a serial output strobe (pin 14). This serial data strobe is not the internal SAR clock but is a special strobe for serial data consisting of 16 negative-going edges (during conversion) occurring about 200ns after each serial data bit is valid. This feature eases the interface to shift registers or through opto- couplers for applications requiring galvanic isolation. STATUS The familiar Status (or Busy) flag, present in successive approximation A/D converters, is available (pin 13) and indicates that a conversion is in progress. Status is valid 110ns after assertion of the convert command (WR low). Status cannot be used as a sample-hold control because there is not enough time for the sample-hold to settle to the required error band before the ADC700 makes its first conversion decision. CHIP SELECT CS (pin 9) selects the ADC700. No other functions can be implemented unless CS is asserted. WR (pin 7) is the start- of-conversion strobe. RD strobes each output data byte, selected by HBEN (pin 10), to the 3-state drivers. LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 16-Bit D/A Converter Successive Approximation Register 20V Range 10V Range Analog Common Digital Common V BTCEN DB15/DB7 DB14/DB6 DB13/DB5 DB12/DB4 DB11/DB3 DB10/DB2 DB9/DB1 DB8/DB0 DD Comparator In Bipolar Offset Gain Adjust Reset WR RD CS HBEN Serial Data Data Ready Status Serial Data Strobe CC +V CC –V All internal control lines not shown. Refer to Figures 4 and 5 for Offset and Gain Adjust connections. Data Latch 3-State Drivers MSB LSB Voltage Reference Clock and Clock Logic 5k Ω 5k Ω MSB Control Logic |
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