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AT88SC153-10CI-00 Datasheet(PDF) 11 Page - ATMEL Corporation |
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AT88SC153-10CI-00 Datasheet(HTML) 11 Page - ATMEL Corporation |
11 / 24 page 11 AT88SC153 1016D–SMEM–04/04 The data byte address lower three bits are internally incremented following the receipt of each data byte. The higher data byte address bits are not incremented, retaining the 8- byte write page address. Each data byte within a page must only be loaded once. Once a stop condition is issued to indicate the end of the host’s write operation, the device ini- tiates the internal nonvolatile write cycle. An ACK polling sequence can be initiated immediately. After a write command, if the host is not allowed to write at some address locations, a nonvolatile write cycle will still be initiated, but the device will only modify data at the allowed addresses. When write lock mode is enabled (WLM = “0”), the write cycle is initiated automatically after the first data byte has been transmitted. Read Fuses Figure 6. Read Fuses Note: Fx = 1: fuse is not blown Fx = 0: fuse is blown The Read Fuses operation is always allowed. The AT88SC153 will continuously trans- mit the fuse byte if the host continues to transmit an ACK. The command is terminated when the host transmits a NACK and STOP bit. Write Fuses Figure 7. Write Fuses Note: nnn = 001 : Blow FAB nnn = 010 : Blow CMA nnn = 100 : Blow PER The Write Fuses operation is only allowed under secure code control; no data byte is transmitted by the host. The fuses are blown sequentially: CMA is blown if FAB is equal to “0”, and PER is blown if CMA is equal to “0”. If the fuses are all “0”s, the operation is canceled and the device waits for a new command. Once a stop condition is issued to indicate the end of the host’s write operation, the device initiates the internal nonvolatile write cycle. An ACK polling sequence can be ini- tiated immediately. 0 S T O P S T A R T |
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