Symbol

Parameter

Conditions

Min

Typ

Max

Units

Propagation Delay Time to

190

300

ns

a Logical ‘‘0’’ or Logical ‘‘1’’ from

75

110

ns

Clock to Q or Q

Propagation Delay Time to a

180

300

ns

Logical ‘‘0’’ from Clear to Q

70

110

ns

Propagation Delay Time to a

230

400

ns

Logical ‘‘1’’ from Clear to Q

90

150

ns

Time Prior to Clock Pulse that

100

45

ns

Data Must be Present

40

16

ns

Time After Clock Pulse that

0

b

11

ns

Data Must be Held

0

b

4ns

Minimum Clock Pulse Width

130

250

ns

45

100

ns

Minimum Clear Pulse Width

120

250

ns

45

100

ns

Maximum Clock Rise Time

15

450

m

s

50

125

m

s

Maximum Clock Fall Time

15

50

m

s

50

50

m

s

Maximum Clock Frequency

20

35

MHz

50

10

MHz

Input Capacitance

Clear Input (Note 2)

10

pF

Any Other Input

50

pF

Power Dissipation Capacitance

Per Package (Note 3)

130

pF

AC Parameters are guaranteed by DC correlated testing

Note 1

‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’

they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device

operation

Note 2

Capacitance is guaranteed by periodic testing

Note 3

AN-90

Switching Time Waveforms

CMOS to CMOS

TLF5900 – 6

3