TLF5902

February 1988

MM54C195MM74C195 4-Bit Registers

General Description

The MM54C195MM74C195 CMOS 4-bit registers feature

parallel inputs parallel outputs J-K serial inputs shiftload

control input and a direct overriding clear The following two

modes of operation are possible

Parallel Load

Parallel loading is accomplished by applying the four bits of

data and taking the shiftload control of input low The data

is loaded into the associated flip-flops and appears at the

outputs after the positive transition of the clock input During

parallel loading serial data flow is inhibited

Serial shifting is accomplished synchronously when the

shiftload control input is high Serial data for this mode is

entered at the J-K inputs These inputs allow the first stage

to perform as a J-K D or T-type flip flop as shown in the

truth table

Features

Y

Medium speed operation

85 MHz (typ) with 10V

supply and 50 pF load

Y

High noise immunity

Y

Low power

100 nW (typ)

Y

Tenth power TTL compatible

Drive 2 LPTTL loads

Y

Supply voltage range

3V to 15V

Y

Synchronous parallel load

Y

Parallel inputs and outputs from each flip-flop

Y

Direct overriding clear

Y

J and K inputs to first stage

Y

Complementary outputs from last stage

Y

Positive-edge triggered clocking

Y

Diode clamped inputs to protect against static charge

Applications

Y

Automotive

Y

Data terminals

Y

Instrumentation

Y

Medical electronics

Y

Alarm systems

Y

Remote metering

Y

Industrial electronics

Y

Computers

Schematic and Connection Diagrams

Pin 8 to GND

TLF5902 – 1

Dual-In-Line Package

TLF5902 – 2

Top View

Order Number MM54C195 or MM74C195

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A