ESDA6V1P6

7/8

3. PCB layout recommendations

As ESD is a fast event, the di/dt caused by this surge is about 30A/ns (risetime=1ns, Ipeak=30A), that

means each nH causes an overvoltage of 30V.

Thus, the circuit board layout is a critical design step in the suppression of ESD induced transients by

reducing parasitic inductances. To ensure that, the following guidelines are recommended :

s

The ESDA6V1P6 should be placed as close as possible to the input terminals or connectors.

s

The path length between the ESD suppressor and the protected line should be minimized.

s

All conductive loops, including power and ground loops should be minimized.

s

The ESD transient return path to ground should be kept as short as possible.

s

The connections from the ground pins to the ground plane should be the shortest possible.

4. Comparison with varistors

Varistors

TRANSIL™

Leakage current

--

+++

Protection efficiency

--

++

Ageing

--

++

Low leakage current for Transil™ device

s

Improve the autonomy of portable equipments as mobile

Better efficiency in terms of ESD protection by using Transil™ device

s

Varistors are bidirectional devices and so are not suitable to protect sensitive ICs, because they will be

submitted to high voltages in the negative way.

s

s

No ageing phenomena regarding ESD events with Transil™ device

s

Higher efficiency in terms of ESD protection

ESDA 6V1 P6

ESD ARRAY

V

min

BR

PACKAGE: SOT-666

ORDER CODE

Ordering type

Marking

Package

Weight

Base qty

Delivery mode

ESDA6V1P6

B

SOT-666

2.9 mg.

3000

Tape & reel