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AS4C32M16MD1A-5BCN Datasheet(PDF) 11 Page - Alliance Semiconductor Corporation

Part # AS4C32M16MD1A-5BCN
Description  60 ball FBGA PACKAGE
Download  53 Pages
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS4C32M16MD1A-5BCN Datasheet(HTML) 11 Page - Alliance Semiconductor Corporation

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5.2 Register Definition
5.2.1 Mode Register
The Mode Register is used to define the specific mode of operation of the LPDDR SDRAM. This definition includes the definition of
a burst length, a burst type, a CAS latency as shown below table.
The Mode Register is programmed via the MODE REGISTER SET command (with BA0=0 and BA1=0) and will retain the stored
information until it is reprogrammed, the device goes into Deep Power-Down mode, or the device loses power.
Mode Register bits A0-A2 specify the burst length, A3 the type of burst (sequential or interleave), A4-A6 the CAS latency. A logic 0
should be programmed to all the undefined addresses bits to ensure future compatibility.
The Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified
time tMRD before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Mode
BA1
BA0
A[n]~A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Standard
MRS
0
0
Reserved
CAS Latency
010b: 2
011b: 3
Burst Type
0:Sequential
1:Interleave
Burst Length
001b :
2
010b
: 4
011b
: 8
100b
: 16
Reserved
0
1
Reserved
Extended
MRS
1
0
Reserved
Drive Strength
000b: Full
Strength Driver
001b: Half
Strength Driver
010b:Quarter
Strength Driver
011b:Octant
Strength Driver
100b:ThreeQuarters
Strength Driver
Reserved
PASR
000b : All banks
001b : 1/2 array(BA1=0)
010b : ¼
array(BA1=BA0=0)
101b : 1/8 array
(BA1 = BA0 = Row Addr MSB =
0)
110b : 1/16 array
(BA1=BA0 = Row Addr 2 MSB
= 0)
Table
5 – Mode Register Table
5.2.1.1 Burst Length
Read and write accesses to the LPDDR SDRAM are burst oriented, with the burst length being set as in Table
5, and the burst order
as in Table
6.
The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command.
Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. A burst length of 16 is
optional and some vendors may choose to implement it.
AS4C32M16MD1A-5BCN
Confidential
- 11/56 -
Rev.1.2 July 2016


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