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IDT5V9950 Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT5V9950 Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 9 page  2 INDUSTRIALTEMPERATURERANGE IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. PIN CONFIGURATION NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Unit VDDQ, VDD Supply Voltage to Ground –0.5 to +4.6 V VI DC Input Voltage –0.5 to VDD+0.5 V REF Input Voltage –0.5 to +5.5 V Maximum Power TA = 85°C 0.7 W Dissipation TA = 55°C 1.1 TSTG Storage Temperature Range –65 to +150 °C NOTE: 1. Capacitance applies to all inputs except TEST, FS, nF[1:0], and DS[1:0]. CAPACITANCE(TA=+25°C,f=1MHz,VIN=0V) Parameter Description Typ. Max. Unit CIN InputCapacitance 5 7 pF 31 10 30 29 28 27 26 25 11 12 13 14 15 16 32 9 1 2 3 4 5 6 7 8 3F1 4F0 4F1 PE 4Q1 4Q0 GND VDDQ 18 GND 24 23 22 21 20 19 sO E 1F1 1F0 1Q0 1Q1 VDDQ 17 GND TQFP TOP VIEW NOTE: 1. When TEST = MID and sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL. PIN DESCRIPTION Pin Name Type Description REF IN ReferenceClockInput FB IN FeedbackInput TEST(1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary Table)remainineffect. SetLOWfornormaloperation. sOE(1) IN Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H) - 2Q0 and 2Q1may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOEis HIGH, the nF[1:0]pinsactasoutput disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull-down). PE IN Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthereference clock(hasinternalpull-up). nF[1:0] IN 3-level inputs for selecting 1 of 9 skew taps or frequency functions FS IN Selectsappropriateoscillatorcircuitbasedonanticipatedfrequencyrange. (SeeProgrammableSkewRange.) nQ[1:0] OUT Fourbanksoftwooutputswithprogrammableskew VDDQ PWR Powersupplyforoutputbuffers VDD PWR Powersupplyforphaselockedloop,lockoutput,andotherinternalcircuitry GND PWR Ground |
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