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MM54HC123A Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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MM54HC123A Datasheet(HTML) 4 Page - National Semiconductor (TI) |
4 / 6 page Logic Diagram TLF5206 – 5 Theory of Operation TLF5206 – 6 j POSITIVE EDGE TRIGGER m POSITIVE EDGE RE-TRIGGER (PULSE LENGTHENING) k NEGATIVE EDGE TRIGGER n RESET PULSE SHORTENING l POSITIVE EDGE TRIGGER o CLEAR TRIGGER FIGURE 1 TRIGGER OPERATION As shown in Figure 1 and the logic diagram before an input trigger occurs the one shot is in the quiescent state with the Q output low and the timing capacitor CEXT completely charged to VCC When the trigger input A goes from VCC to GND (while inputs B and clear are held to VCC) a valid trig- ger is recognized which turns on comparator C1 and N- channel transistor N1 j At the same time the output latch is set With transistor N1 on the capacitor CEXT rapidly dis- charges toward GND until VREF1 is reached At this point the output of comparator C1 changes state and transistor N1 turns off Comparator C1 then turns off while at the same time comparator C2 turns on With transistor N1 off the capacitor CEXT begins to charge through the timing re- 4 |
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