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IDT70V7519S133BC Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT70V7519S133BC Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 22 page  6.42 6 IDT70V7519S High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, REPEAT are set as appropriate for address access. Refer to Truth Table II for details. 3. OE is an asynchronous input signal. 4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here. Truth Table IRead/Write and Enable Control(1,2,3,4) OE3 CLK CE0 CE1 BE3 BE2 BE1 BE0 R/ W Byte 3 I/O27-35 Byte 2 I/O18-26 Byte 1 I/O9-17 Byte 0 I/O0-8 MODE X ↑ H XXXXX XHigh-Z High-Z High-Z High-Z Deselected–Power Down X ↑ X L XXXX XHigh-Z High-Z High-Z High-Z Deselected–Power Down X ↑ L H HHHH X High-Z High-Z High-Z High-Z All Bytes Deselected X ↑ L H H H H L L High-Z High-Z High-Z DIN Write to Byte 0 Only X ↑ LH H H LH L High-Z High-Z DIN High-Z Write to Byte 1 Only X ↑ LH H L H H L High-Z DIN High-Z High-Z Write to Byte 2 Only X ↑ LH LH H H L DIN High-Z High-Z High-Z Write to Byte 3 Only X ↑ L H H H L L L High-Z High-Z DIN DIN Write to Lower 2 Bytes Only X ↑ LH L L H H L DIN DIN High-Z High-Z Write to Upper 2 bytes Only X ↑ L H LLLLL DIN DIN DIN DIN Write to All Bytes L ↑ L H H H H L H High-Z High-Z High-Z DOUT Read Byte 0 Only L ↑ L H H H L H H High-Z High-Z DOUT High-Z Read Byte 1 Only L ↑ L H H L H HHHigh-Z DOUT High-Z High-Z Read Byte 2 Only L ↑ LH LH H H H DOUT High-Z High-Z High-Z Read Byte 3 Only L ↑ L H H H L L H High-Z High-Z DOUT DOUT Read Lower 2 Bytes Only L ↑ LH L L H H H DOUT DOUT High-Z High-Z Read Upper 2 Bytes Only L ↑ L H LLLL H DOUT DOUT DOUT DOUT Read All Bytes H X X XXXXX XHigh-Z High-Z High-Z High-Z Outputs Disabled 5618 tbl 02 Truth Table IIAddress and Address Counter Control(1,2,7) NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/ W, CE0, CE1, BEn and OE. 3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn. 6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location. 7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer to Timing Waveform of Counter Repeat, page 18. Care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA0L - BA5L ≠ BA0R - BA5R), as this condition will invalidate the access for both ports. Please refer to the functional description on page 19 for details. Address Previous Address Addr Used CLK ADS CNTEN REPEAT(6) I/O(3) MODE An X An ↑ L(4) XH DI/O (n) External Address Used XAn An + 1 ↑ H L(5) HDI/O(n+1) Counter Enabled—Internal Address generation X An + 1 An + 1 ↑ HH H DI/O(n+1) External Addre ss Blocked—Counter disab led (An + 1 reused) XX An ↑ XX L(4) DI/O(0) Counter Set to last valid ADS load 5618 tbl 03 |
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