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IDT72V12081L15PFI Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT72V12081L15PFI Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 9 page  2 IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 INDUSTRIALTEMPERATURERANGE Symbol Name I/O Description D0-D7 Data Inputs I Data inputs for a 8-bit bus. EF Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. FF Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. OE OutputEnable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. Q0-Q7 DataOutputs O Data outputs for a 8-bit bus. RCLK Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted. REN Read Enable I When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. RS Reset I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF goes HIGH, and EF goes LOW. A Reset is required before an initial Write after power-up. WCLK WriteClock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable is asserted. WEN WriteEnable I When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. Data will not be written into the FIFO if the FF is LOW. VCC Power I 3.3V volt power supply. GND Ground I Ground pin. TQFP (PR32-1, order code: PF) TOP VIEW PIN CONFIGURATION PIN DESCRIPTIONS WEN WCLK VCC VCC Q1 Q2 Q3 5 6 7 8 16 D6 GND RCLK GND D7 27 26 25 24 23 22 21 29 28 32 31 30 9 1011 1213 1415 6161 drw02 1 2 3 4 20 19 18 17 INDEX Q0 REN DNC(1) DNC(1) NOTE: 1. DNC = Do Not Connect. |
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