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IDT72V215L10PFI Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT72V215L10PFI Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 25 page 7 IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES The contents of the offset registers can be read on the data output lines Q0- Q11 when the LD pin is set LOW and REN is set LOW. Data can then be read on the next LOW-to-HIGH transition of RCLK. The first transition of RCLK will presenttheemptyoffsetvaluetothedataoutputlines.ThenexttransitionofRCLK willpresentthefulloffsetvalue.OffsetregistercontentcanbereadoutintheIDT Standard mode only. It cannot be read in the FWFT mode. SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIM- ING SELECTION The IDT72V205/72V215/72V225/72V235/72V245 can be configured during the "Configuration at Reset" cycle described in Table 3 with either asynchronous or synchronous timing for PAE and PAF flags. If asynchronous PAE/PAF configuration is selected (as per Table 3), the PAEisassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAEisresetto HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAFisasserted LOWontheLOW-to-HIGHtransitionofWCLKand PAFisresettoHIGHonthe LOW-to-HIGHtransitionofRCLK.Fordetailtimingdiagrams,seeFigure13for asynchronous PAE timing and Figure 14 for asynchronous PAF timing. Ifsynchronous PAE/PAFconfigurationisselected,thePAEisassertedand updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Fordetail timing diagrams, see Figure 22 for synchronous PAEtimingandFigure23for synchronous PAFtiming. REGISTER-BUFFERED FLAG OUTPUT SELECTION The IDT72V205/72V215/72V225/72V235/72V245 can be configured duringthe"ConfigurationatReset"cycledescribedinTable4withsingle,double or triple register-buffered flag output signals. The various combinations avail- able are described in Table 4 and Table 5. In general, going from single to double or triple buffered flag outputs removes the possibility of metastable flag indicationsonboundarystates(i.e,emptyorfullconditions).Thetrade-offisthe addition of clock cycle delays for the respective flag to be asserted. Not all combinationsof register-bufferedflagoutputsaresupported.Register-buffered outputsapplytotheEmptyFlagandFullFlagonly. Partialflagsarenoteffected. Table 4 and Table 5 summarize the options available. Number of Words in FIFO IDT72V205 IDT72V215 IDT72V225 IDT72V235 IDT72V245 FF PAF HF PAE EF 00 0 0 0 H H H L L 1 to n(1) 1 to n(1) 1 to n(1) 1 to n(1) 1 to n(1) HH H L H (n + 1) to 128 (n + 1) to 256 (n + 1) to 512 (n + 1) to 1,024 (n + 1) to 2,048 H H H H H 129 to (256-(m+1))(2) 257 to (512-(m+1))(2) 513 to (1,024-(m+1))(2) 1,025 to (2,048-(m+1))(2) 2,049 to (4,096-(m+1))(2) HH L H H (256-m)to255 (512-m)to511 (1,024-m)to1,023 (2,048-m)to2,047 (4,096-m)to4,095 H L L H H 256 512 1,024 2,048 4,096 L L L H H TABLE 1 STATUS FLAGS FOR IDT STANDARD MODE TABLE 2 STATUS FLAGS FOR FWFT MODE Number of Words in FIFO IDT72V205 IDT72V215 IDT72V225 IDT72V235 IDT72V245 IR PAF HF PAE OR 00 0 0 0 L H H L H 1 to (n + 1)(1) 1 to (n + 1)(1) 1 to (n + 1)(1) 1 to (n + 1)(1) 1 to (n + 1)(1) LHH L L (n + 2) to 129 (n + 2) to 257 (n + 2) to 513 (n + 2) to 1,025 (n + 2) to 2,049 L H H H L 130 to (257-(m+1))(2) 258 to (513-(m+1))(2) 514 to (1,025-(m+1))(2) 1,026 to (2,049-(m+1))(2) 2,050 to (4,097-(m+1))(2) LH LH L (257-m) to 256 (513-m) to 512 (1,025-m) to 1,024 (2,049-m) to 2,048 (4,097-m) to 4,096 LL L H L 257 513 1,025 2,049 4,097 H L L H L NOTES: 1. n = Empty Offset (Default Values : IDT72V205 n = 31, IDT72V215 n = 63, IDT72V225/72V235/72V245 n = 127) 2. m = Full Offset (Default Values : IDT72V205 m = 31, IDT72V215 m = 63, IDT72V225/72V235/72V245 m = 127) NOTES: 1. n = Empty Offset (Default Values : IDT72V205 n=31, IDT72V215 n = 63, IDT72V225/72V235/72V245 n = 127) 2. m = Full Offset (Default Values : IDT72V205 m=31, IDT72V215 m = 63, IDT72V225/72V235/72V245 m = 127) |
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