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MM58167 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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MM58167 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 10 page Functional Description (Continued) Typical Supply Current vs Supply Voltage Standby Interrupt during Power Down Typical Characteristics TLF11070 – 4 TLF11070 – 5 FIGURE 2 Interrupt Timing 0 C s TA s 70 C 45V s VDD s 55V VSS e 0V Symbol Parameter Min Max Units tINTON Status Register Clock to INTERRUPT OUTPUT 5 m s (Pin 13) High (Note 1) tSBYON Compare Valid to STANDBY INTERRUPT 5 m s (Pin 14) Low (Note 1) tINTOFF Trailing Edge of Status Register 5 m s Read to INTERRUPT OUTPUT Low tSBYOFF Trailing Edge of Write Cycle (D0 e 0 Address e 16H) to STANDBY 5 m s INTERRUPT Off (High Impedance State) Note 1 The status register clocks are the corresponding counter’s rollover to its reset state or the compare becoming valid The compare becomes valid 61 ms after the 110000 of a second counter is clocked if the real time counter data matches the RAM data Read Cycle Timing 0 C s TA s 70 C 45V s VDD s 55V VSS e 0V Symbol Parameter Min Max Units tAR Address Bus Valid to Read Strobe (Note 3) 100 ns tCSR Chip Select to Read Strobe (Note 2) 0 ns tRRY Read Strobe to Ready Strobe 150 ns tRYD Ready Strobe to Data Valid 800 ns tAD Address Bus Valid to Data Valid 1050 ns tRH Data Hold Time from Trailing Edge of Read Strobe 0 ns tHZ Trailing Edge of Read Strobe to TRI-STATE Mode 250 ns tRYH Read Hold Time after Ready Strobe 0 ns tRA Address Bus Hold Time from Trailing Edge of Read Strobe 50 ns tRYDV Rising Edge of Ready to Data Valid 100 ns Note 2 When reading a deselect time of 500 ns minimum must occur between counter reads Deselect is CS e 1or(WR) (RD) e 1 Note 3 If tAR e 0 and Chip Select Address Valid or Read are coincident then they must exist for 1050 ns 6 |
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