SiC533

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Vishay Siliconix

S16-2309-Rev. A, 14-Nov-16

11

Document Number: 75010

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Step 5: Signal Routing

1. Route the PWM and ZCD_EN# signal traces out of the

top left corner next to pin 1.

2. The PWM signal is an important signal, both signal and

return traces should not cross any power nodes on any

layer.

3. It is best to “shield” these traces from power switching

integrity.

4. GL (pin 19) has been connected with GL pad (pin 24)

internally.



Step 6: Adding Thermal Relief Vias

pads to utilize inner layers for high-current and thermal

dissipation.

2. To achieve better thermal performance, additional vias

place vias on this pad.

4. 8 mil vias for pads and 10 mils vias for planes are the

optimal via sizes. Vias on pad may drain solder during

assembly and cause assembly issues. Consult with the

assembly house for guidelines.

Step 7: Ground Connection

1. It is recommended to make a single connection between

2. It is recommended to make the entire first inner layer

(below top layer) the ground plane and separate them

3. These ground planes provide shielding between noise

sources on top layer and signal traces on bottom layer.