SiC462

www.vishay.com

Vishay Siliconix

S17-0360-Rev. D, 13-Mar-17

8

Document Number: 65124

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Power-Save Mode, MODE Pin, and Ultrasonic Pin

Operation

To improve efficiency at light-loads, SiC462 provides a set

of innovative implementations to eliminate LS re-circulating

current and switching losses. The internal zero crossing

detector (ZCD) monitors SW node voltage to determine

when inductor current starts to flow negatively. In power

saving mode, as soon as inductor valley current crosses

zero, the device first deploys diode emulation mode by

turning off the LS FET. If load further decreases, switching

frequency is reduced proportional to the load condition to

save switching losses while keeping output ripple within

switching frequency in the discontinuous mode is 25 kHz to

avoid switching frequencies in the audible range. If this

feature is not required this ultrasonic mode can be disabled

by floating the ultrasonic pin. When the ultrasonic mode is

disabled, the regulator will either operate in forced

continuous mode or in a power save mode where there is no

limit to the lower frequency limit. In this state, at zero load

switching frequency can go as low as hundreds of Hz.

To improve the converter efficiency, the user can choose to

reduces power dissipation in the SiC462 by eliminating the

The MODE pin supports several modes of operation as

shown in table 1. An internal current source is used to set

the voltage on this pin using an external resistor:

Note

The mode pin is not latched to any state and can be

changed on the fly.

OUTPUT

MONITORING

AND

PROTECTION

FEATURES

Output Over-Current Protection (OCP)

SiC462 has cycle by cycle current limiting. The inductor

valley current is monitored during LS FET turn-on period

the valley current is compared with an internal threshold. If

monitored current is higher than threshold, HS turn-on pulse

is skipped and LS FET is kept on until the valley current

returns below OCP limit.

In a short circuit or a severe over-current condition, output

undervoltage protection (UVP) will result in both the HS and

LS FET turning off. See output undervoltage protection

(UVP) section for more details.

Fig. 6 - Over-Current Protection Illustration

Output Undervoltage Protection (UVP)

recognized and both HS and LS MOSFETs are turned off.

After a time-out period equal to 20 soft start cycles, the IC

attempts to re-start by going through a soft start cycle. If the

fault condition still exists, the above cycle will be repeated.

UVP is only active after the completion of soft-start

sequence.

Output Over-Voltage Protection (OVP)

For OVP implementation, output is monitored through FB

pin. After soft start, if the voltage level at FB is above 0.96 V

both the HS and LS MOSFETs turned off. Normal operation

is resumed once FB voltage drops back to 0.96 V.

Over-Temperature Protection (OTP)

SiC462 has internal thermal monitor block that turns off both

HS and LS FETs when junction temperature is above 150 °C

(typ). A hysteresis of 35 °C is implemented, so when junction

temperature drops below 115 °C, the device restarts by

initiating soft-start sequence again.

Sequencing of Input / Output Supplies

SiC462 has no sequencing requirements on any of its

Enable

The SiC462 has an enable pin to turn the part on and off.

Driving this pin high enables the device, while grounding it

turns it off.

The SiC462 enable has a weak pull down to prevent

unwanted turn on due to a floating GPIO.

There

are

no

sequencing

requirements

w.r.t

other

input / output supplies.



TABLE 1 - OPERATION MODES

MODE

RANGE (V)

POWER SAVE

MODE

REGULATOR

1

0 to 0.7

Enabled

ON

2

1.3 to 1.7

Disabled

ON

3

2.3 to 2.7

Disabled

4

Enabled

R

LIM

480k / I

OUT max.

=

I

load

OCP

threshold

I

inductor

GH