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LT5546EUF Datasheet(PDF) 10 Page - Linear Technology

Part # LT5546EUF
Description  40MHz to 500MHz VGA and I/Q Demodulator with 17MHz Baseband Bandwidth
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LT5546EUF Datasheet(HTML) 10 Page - Linear Technology

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LT5546
10
5546f
Table 2. The Logic of Different Operating Modes
EN
STBY
Comments
Low
Low
Shutdown Mode
Low
High
Standby Mode
High
Low or High
Normal Operation Mode
APPLICATIO S I FOR ATIO
up recovery from an overload event, which can occur
during the gain settling. The clipping level is approxi-
mately constant over temperature. The first order inte-
grated lowpass filters are used for noise filtering of the
down-converted baseband signals for both the I channel
and the Q channel. These filters are well matched in gain
response. The –3dB corner frequency is typically 17MHz.
The I/Q outputs can drive 2k
Ω in parallel with a maximum
capacitive loading of 10pF at 5MHz, from all four pins to
ground. The outputs are internally biased at VCC – 1.19V.
Figure 5 shows the simplified output circuit schematic of
the I channel or Q channel.
The I/Q baseband outputs can be DC-coupled to the inputs
of a baseband chip. For AC-coupled applications with large
capacitors, the STBY pin can be used to pre-bias the
outputs to nominal VCC – 1.19V at much reduced current.
This mode draws only 3.6mA supply current. When the EN
pin is then driven high (>1V), the chip is quickly switched
to normal operating mode, avoiding the introduction of
large charging time constants. Table 2 shows the logic of
the EN pin and STBY pin. In both normal operating mode
Figure 5. Simplified Circuit Schematic of I Channel
(or Q Channel) Outputs and STBY (or EN) Input
300
µA
300
µA
VCC
I CHANNEL (OR
Q CHANNEL):
DIFFERENTIAL
SIGNALS
FROM LPF
IOUT
+
(OR QOUT
+)
IOUT
(OR QOUT
)
5546 F05
STBY
(OR EN)
VCC
22k
and standby mode, the maximum discharging current is
about 300
µA, and the maximum charging current is more
than 4mA. In Figure 5 the simplified circuit schematic of
the STBY (or EN) input is shown.
Figure 6. Evaluation Circuit Schematic with I/Q Output Buffers
+
1
2
3
4
12
11
10
9
STBY
2XLO+
2XLO
EN
GND
IF+
IF
GND
U1
LT5546
T1, 1:4,TR-R
JTX-4-10T
MINI-CIRCUITS
IFIN
R48
3.09k
R47
49.9
R51
100
C32
1pF
R40
3.09k
C29
1pF
R52
240
R36
20k
R35
20k
C34
0.1
µF
C35
4.7
µF
C38
0.1
µF
C37
0.1
µF
C1
5.6pF
C2
5.6pF
SW1
1 = EN
2 = STBY
1
6
1
6
+
C45
22nF
7
7
6
6
4
4
3
2
3
2
J1
IOUT
IOUT
+ I
OUT
Q
OUT
+ Q
OUT
IOUT
+ I
OUT
Q
OUT
+ Q
OUT
QOUT
J3
J4
C22
1
µF
C33
0.1
µF
C31
1
µF
R44
49.9
J2
C30
1
µF
U3
LT1818CS
U2
LT1818CS
VCC1
VCC2
VCTRL
VCC VCTRL
VCC
C26
1.8pF
C25
1.5pF
C16
1nF
C15
1nF
C39
1
µF
VCC3
C36
4.7
µF
R46
3.09k
R45
1k
C28
0.1
µF
R42
2k
R49
2k
R39
3.09k
R41
1k
R50
2k
C27
0.1
µF
R43
2k
2XLO
OVERLOAD
IF
DET
16
15
14
13
5
6
7
8
17
GND
NOTE: OUTPUT BUFFERS U2 AND U3 WITH ASSOCIATED
COMPONENTS ARE INCLUDED FOR EVALUATION ONLY.
DEMO BOARD: DC696A
C43, C45, C22, R51, C25, C26 AND C39 ARE OPTIONAL
5546 F04
T2, 1:4, TR-R
JTX-4-10T
MINI-CIRCUITS
C43
22nF
5V
OPTIONAL


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