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AK5558VN Datasheet(PDF) 59 Page - Asahi Kasei Microsystems |
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AK5558VN Datasheet(HTML) 59 Page - Asahi Kasei Microsystems |
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59 / 70 page  [AK5558] 015099850-E-00 2016/03 - 59 - (2) I 2C-bus Control Mode (I2C pin = “H” and PSN pin = “L”) The AK5558 supports the fast-mode I2C-bus (max: 400 kHz, Ver1.0). (2)-1. WRITE Operations Figure 63 shows the data transfer sequence of the I2C-bus control mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 69). After the START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave address are fixed as “00100”. The next bits are CAD1-0 (device address bits). This bits identifies the specific device on the bus. The hard-wired input pins (CAD1-0 pins) set these device address bit (Figure 64). If the slave address matches that of the AK5558, the AK5558 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 70 ). R/W bit = “1” indicates that the read operation is to be executed. “0” indicates that the write operation is to be executed. The second byte consists of the control register address of the AK5558. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 65). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 66). The AK5558 generates an acknowledge after each byte is received. Data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition (Figure 69). The AK5558 can perform more than one byte write operation per sequence. After receipt of the third byte the AK5558 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the addres s exceeds “07H” prior to generating a stop condition, the address counter will “roll over” to “00H” and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 71) except for the START and STOP conditions. 3rd byte 2nd byte 1st byte SDA S T A R T A C K A C K S Slave Address A C K Sub Address(n) Data(n) P S T O P Data(n+x) A C K Data(n+1) A C K R/W= “0” A C K Figure 63. Data Transfer Sequence at the I 2C-Bus Control Mode 0 0 1 0 0 CAD1 CAD0 R/W (CAD0 and CAD1 are set by pins) Figure 64. The First Byte 0 0 0 A4 A3 A2 A1 A0 Figure 65. The Second Byte D7 D6 D5 D4 D3 D2 D1 D0 Figure 66. Byte Structure After The Second Byte |
Similar Part No. - AK5558VN_16 |
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Similar Description - AK5558VN_16 |
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