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AK7735EQ Datasheet(PDF) 42 Page - Asahi Kasei Microsystems |
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AK7735EQ Datasheet(HTML) 42 Page - Asahi Kasei Microsystems |
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42 / 142 page  [AK7735] 016014707-E-00 2016/12 - 42 - BDVx[9:0] bits MBICKx Dividing MBICKx(MHz) SDVx[2:0] bits MLRCKx Dividing MLRCKx(kHz) 48kHz Base 44.1kHz Base 48kHz Base 44.1kHz Base 0x23F 576 0.256 0.2352 010 32 8 N/A 0x17F 384 0.384 0.3528 001 48 8 N/A 0x11F 288 0.512 0.4704 000 64 8 N/A 0x08F 144 1.024 0.9408 011 128 8 N/A 0x047 72 2.048 1.8816 100 256 8 N/A 0x17F 384 0.384 0.3528 010 32 12 11.025 0x0FF 256 0.576 0.5292 001 48 12 11.025 0x0BF 192 0.768 0.7056 000 64 12 11.025 0x05F 96 1.536 1.4112 011 128 12 11.025 0x02F 48 3.072 2.8224 100 256 12 11.025 0x11F 288 0.512 0.4704 010 32 16 14.7 0x0BF 192 0.768 0.7056 001 48 16 14.7 0x08F 144 1.024 0.9408 000 64 16 14.7 0x047 72 2.048 1.8816 011 128 16 14.7 0x023 36 4.096 3.7632 100 256 16 14.7 0x0BF 192 0.768 0.7056 010 32 24 22.05 0x07F 128 1.152 1.0584 001 48 24 22.05 0x05F 96 1.536 1.4112 000 64 24 22.05 0x02F 48 3.072 2.8224 011 128 24 22.05 0x017 24 6.144 5.6448 100 256 24 22.05 0x08F 144 1.024 0.9408 010 32 32 29.4 0x05F 96 1.536 1.4112 001 48 32 29.4 0x047 72 2.048 1.8816 000 64 32 29.4 0x023 36 4.096 3.7632 011 128 32 29.4 0x011 18 8.192 7.5264 100 256 32 29.4 0x05F 96 1.536 1.4112 010 32 48 44.1 0x03F 64 2.304 2.1168 001 48 48 44.1 0x02F 48 3.072 2.8224 000 64 48 44.1 0x017 24 6.144 5.6448 011 128 48 44.1 0x00B 12 12.288 11.2896 100 256 48 44.1 0x02F 48 3.072 2.8224 010 32 96 88.2 0x01F 32 4.608 4.2336 001 48 96 88.2 0x017 24 6.144 5.6448 000 64 96 88.2 0x00B 12 12.288 11.2896 011 128 96 88.2 0x005 6 24.576 22.5792 100 256 96 88.2 0x017 24 6.144 5.6448 010 32 192 176.4 0x00F 16 9.216 8.4672 001 48 192 176.4 0x00B 12 12.288 11.2896 000 64 192 176.4 0x005 6 24.576 22.5792 011 128 192 176.4 Table 11. Clock Sync Domain Setting when PLLMCLK is Clock Source (N/A: Not Available) For Clock Sync Domain, set BDVx[9:0] bits and SDVx[2:0] bits according to the input clock frequency when the XTI or BICK pin input is selected as the clock source, as well as the PLLMCLK. MBICKx = XTI pin or BICKx pin frequency divided by BDVx[9:0] bits setting MLRCKx = MBICKx divided by SDVx[2:0] bits setting |
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