[AK7758]

016003563-E-02-PB

2016/09

- 22 -

8.5. Switching Characteristics

8.5.1. System Clock

(Ta= -40~85°C; AVDD=3.0~3.6V, TVDD1/2=1.7~3.6V, DVDD=1.14~1.3V, AVSS=DVSS=0V,

CL=20pF)

Parameter

Symbol

Min.

Typ.

Max.

Unit

with Crystal Oscillator

Input Frequency

fXTI

11.2896

18.432

MHz

with External Clock

Duty Cycle

40

50

60

%

Input Frequency

fXTI

11.0

18.6

MHz

LRCK Frequency

(Note 43)

fs

8

48

kHz

BICK Frequency

(Note 44)

Normal Interface

High Level Width

tBCLKH

128

ns

Low Level Width

tBCLKL

128

ns

Frequency

fBCLK

0.23

3.072

3.1

MHz

TDM Interface

High Level Width

tBCLKH

32

ns

Low Level Width

tBCLKL

32

ns

Frequency

fBCLK

1.8

12.288

12.3

MHz

Note 43. LRCK frequency and sampling rate (fs) should be the same.

Note 44. When BICK is the source of the master clock, it should be synchronized to LRCK and have

stable frequency.

1/fs

1/fs

VIH

VIL

tBCLKL

tBCLKH

1/fBCLK

1/fBCLK

VIH

VIL

tBCLK=1/fBCLK

ts=1/fs

LRCK

BICK

1/fXTI

1/fXTI

VIH

VIL

XTI

tXTI=1/fXTI

Figure 6. System Clock Timing