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PE42742MLIBB-Z Datasheet(PDF) 8 Page - Peregrine Semiconductor |
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PE42742MLIBB-Z Datasheet(HTML) 8 Page - Peregrine Semiconductor |
8 / 10 page Product Specification PE42742 Page 8 of 10 ©2006-2012 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0203-07 │ UltraCMOS™ RFIC Solutions Evaluation Kit The SPDT Switch Evaluation Kit facilitates customer evaluation of the PE42742 SPDT switch. The RF common port is connected through a 75 Ω transmission line to J2. Ports 1 and 2 are connected through 75 Ω transmission lines to J1 and J3. A through line connects F connectors J4 and J5. This transmission line can be used to estimate the PCB loss over the environmental conditions. J6 provides DC and digital inputs to the device. The board is composed of a two metal layer FR4 material with a total thickness of 0.032”. The transmission lines are hybrid microstrip/coplanar waveguide with ground plane (28 mil core, 12 mil width, 12 mil gap). The provided jumpers short the control pins to ground for logic low. With the jumper removed the control input rises to VDD for logic high through the 1 MΩ pull up resistor. These resistors will draw several microamps from VDD. They are not required for normal operation. Figure 18. Evaluation Board Layouts Figure 19. Evaluation Board Schematic Peregrine Specification 102/0352 Peregrine Specification 101/0269 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com |
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