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QPO-2 Data Sheet Rev. 1.6 Page 7 of 11

The line inductance from the output of the QPO-2 to the

load should be minimized. This inductance will cause

voltage spikes and ringing proportional to the inductance

and the rate of change in the transient load current. This

effect is outside the control of the QPO-2 and may require

low ESR capacitance placed at the switching load when

long lines exists between the QPO-2 output and reference

ground and load. The rate of load change should be less

than 1 Amp per microsecond to minimize excessive

voltage ringing during the di/dt. The line inductance

between the power supply output and QPO input should

also follow low inductance layout practices.

The user must be aware of the converter’s over-voltage set

point and not create a headroom voltage that will cause a

shutdown condition. For this reason it is recommended

that the QPO-2 be used with power supplies running at

the factory pre-set voltages or in a trimmed down

configuration.

SC/Trim Adjustment

The RSC resistor is tied between QPOOUT and SC SET pin

and controls the correction current used to trim the

converter to compensate for the headroom voltage.

The value for the SC SET resistor is calculated by the

following equation:

input of the converter (4)

SC or TRIM.

This feature can be used in conjunction with an initially

trimmed down supply.

Note 4: When applicable consider the equivalent impedance of

the SC/Trim pin after a trimmed down adjustment has been made

to the supply. Use the power supply manufacturer’s trim down

procedure by connecting a resistor from the SC/Trim pin to

ground.

The active loop performance of the QPO-2 has been

optimized to provide adequate phase margin over a worse

case load impedance range. Loading the QPO-2 directly

with low ESR ceramic capacitance however will

significantly reduce the phase margin and is not

recommended. The effects of the typical distributed

inductance of the load path will mitigate the reduction in

phase margin when low ESR ceramic capacitors are

dispersed about the load path. Tantalum and Electrolytic

capacitors are higher ESR components and are not a

concern for phase margin.

When using the QPO as shown in Figure 4 the CSC

capacitor creates a soft starting of the headroom

correction current being sourced into the SC/Trim input of

the converter, preventing the output from tripping the

over voltage function while the QPO-2 output reaches

regulation. The QPO-2 ramp up time is typically 5 to 10

milliseconds. The CSC value will be supply dependent but

is typically around 1 to 10 µF.

of the converter from CSC as well as limit the correction

current to a level below what will cause an OVP trip

condition during start up. The compliance of the SC

formula below can be used to limit the worst-case

correction current below the maximum trim up

specification of the converter being used. Note the

for proper headroom correction.

Headroom Slope Adjustment

This feature can be used to allow more headroom at

lighter loads inceasing the delta voltage available to

improve transient load capability, while approximating

constant power dissipation of the QPO-2 over the full load

range. The slope of this curve is set by the slope adjust

resistance versus power dissipation for a load current of 10

Amps. The same data is plotted in Figure 10 with the slope

adjust feature reducing the headroom by 150 mV over the

was selected at the minimum load condition while

This feature is useful in improving the QPO-2 efficiency