DVDD

DGND

CLKIN

GAIN

CAP

CAP

AINP

AINN

DRDY/DOUT

SCLK

PDWN

SPEED

AVDD

AGND

REFP

REFN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ADS1230

ADS1230

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SBAS366B – OCTOBER 2006 – REVISED SEPTEMBER 2012

PIN CONFIGURATION

PW PACKAGE

TSSOP-16

(Top View)

PIN DESCRIPTIONS

ANALOG/DIGITAL

NAME

TERMINAL

INPUT/OUTPUT

DESCRIPTION

DVDD

1

Digital

Digital Power Supply: 2.7V to 5.3V

DGND

2

Digital

Digital Ground

CLKIN

3

Digital/Digital Input

External Clock Input: typically 4.9152MHz. Tie low to activate internal oscillator.

PGA Gain Select

GAIN

PGA

GAIN

4

Digital Input

0

64

1

128

CAP

5

Analog

Gain Amp Bypass Capacitor Connection

CAP

6

Analog

Gain Amp Bypass Capacitor Connection

AINP

7

Analog Input

Positive Analog Input

AINN

8

Analog Input

Negative Analog Input

REFN

9

Analog Input

Negative Reference Input

REFP

10

Analog Input

Positive Reference Input

AGND

11

Analog

Analog Ground

AVDD

12

Analog

Analog Power Supply, 2.7V to 5.3V

Data Rate Select:

SPEED

DATA RATE

SPEED

13

Digital Input

0

10SPS

1

80SPS

PDWN

14

Digital Input

Power-Down: Holding this pin low powers down the entire converter and resets the ADC.

Serial Clock: Clock out data on the rising edge. Also used to initiate Offset Calibration and Sleep

SCLK

15

Digital Input

modes. See the Offset Calibration, Standby Mode, and Standby Mode with Offset Calibration sections

for more details.

Dual-Purpose Output:

DRDY/DOUT

16

Digital Output

Data Ready: Indicates valid data by going low.

Data Output: Outputs data, MSB first, on the first rising edge of SCLK.

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