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66AK2H06DAAW24 Datasheet(PDF) 8 Page - Texas Instruments

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Part # 66AK2H06DAAW24
Description  Multicore DSPARM KeyStone II System-on-Chip (SoC)
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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66AK2H06DAAW24 Datasheet(HTML) 8 Page - Texas Instruments

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66AK2H14/12/06
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.
SPRS866E—November 2012—Revised November 2013
Contents
1
66AK2H14/12/06 Features and Description. . . . . . . . . . .1
1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.2
Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.3
KeyStone Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.4
Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.5
Enhancements in KeyStone II . . . . . . . . . . . . . . . . . . . . . . . . .3
1.6
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.7
Release History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2
C66x DSP CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3
ARM CorePac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4
Development Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.1
Development Support . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5
Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6
Related Documentation from Texas Instruments . . . . 19
3
C66x CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.1
L1P Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.2
L1D Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.3
L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.4
Multicore Shared Memory SRAM . . . . . . . . . . . . . . 24
3.1.5
L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2
Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3
Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4
Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5
C66x CorePac Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.6
C66x CorePac Register Descriptions . . . . . . . . . . . . . . . . . 26
4
ARM CorePac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3
ARM Cortex-A15 Processor. . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3.3
ARM Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . 31
4.3.4
Endianess. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4
CFG Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.5
Main TeraNet Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.6
Clocking and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.6.1
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.6.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5
Terminals
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1
Package Terminals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.1
Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3
Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6
Memory, Interrupts, and EDMA for 66AK2H14/12/06 82
6.1
Memory Map Summary for 66AK2H14/12/06 . . . . . . . . 82
6.2
Memory Protection Unit (MPU) for 66AK2H14/12/06. 95
6.2.1
MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.2.2
MPU Programmable Range Registers . . . . . . . . . 102
6.3
Interrupts for 66AK2H14/12/06 . . . . . . . . . . . . . . . . . . . . 110
6.3.1
Interrupt Sources and Interrupt Controller . . . . 110
6.3.2
CIC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
6.3.3
Inter-Processor Register Map . . . . . . . . . . . . . . . . . 176
6.3.4
NMI and LRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.4
Enhanced Direct Memory Access (EDMA3) Controller for
66AK2H14/12/06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
6.4.1
EDMA3 Device-Specific Information . . . . . . . . . . .179
6.4.2
EDMA3 Channel Controller Configuration . . . . .179
6.4.3
EDMA3 Transfer Controller Configuration . . . . .179
6.4.4
EDMA3 Channel Synchronization Events . . . . . .180
7
System Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
7.1
Internal Buses and Switch Fabrics . . . . . . . . . . . . . . . . . . .189
7.2
Switch Fabric Connections Matrix - Data Space. . . . . .190
7.3
TeraNet Switch Fabric Connections Matrix -
Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
7.4
Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
8
Device Boot and Configuration . . . . . . . . . . . . . . . . . . . .203
8.1
Device Boot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
8.1.1
Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
8.1.2
Boot Modes Supported . . . . . . . . . . . . . . . . . . . . . . .205
8.1.3
SoC Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
8.1.4
System PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . .227
8.2
Device Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
8.2.1
Device Configuration at Device Reset . . . . . . . . .229
8.2.2
Peripheral Selection After Device Reset. . . . . . . .230
8.2.3
Device State Control Registers . . . . . . . . . . . . . . . .230
9
Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . .262
9.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .262
9.2
Recommended Operating Conditions . . . . . . . . . . . . . .263
9.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
9.4
Power Supply to Peripheral I/O Mapping. . . . . . . . . . . .265
10
66AK2H14/12/06 Peripheral Information and
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .266
10.1
Recommended Clock and Control Signal Transition
Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
10.2
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
10.2.1
Power-Up Sequencing. . . . . . . . . . . . . . . . . . . . . . .267
10.2.2
Power-Down Sequence. . . . . . . . . . . . . . . . . . . . . .273
10.2.3
Power Supply Decoupling and Bulk
Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
10.2.4
SmartReflex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
10.3
Power Sleep Controller (PSC) . . . . . . . . . . . . . . . . . . . . . .276
10.3.1
Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
10.3.2
Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
10.3.3
PSC Register Memory Map . . . . . . . . . . . . . . . . . . .278
10.4
Reset Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
10.4.1
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
10.4.2
Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284
10.4.3
Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
10.4.4
Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
10.4.5
ARM CorePac Reset. . . . . . . . . . . . . . . . . . . . . . . . . .286
10.4.6
Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
10.4.7
Reset Controller Register . . . . . . . . . . . . . . . . . . . .286
10.4.8
Reset Electrical Data/Timing . . . . . . . . . . . . . . . . .286
10.5
Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL,
PASS PLL and the PLL Controllers. . . . . . . . . . . . . . . . .288
10.5.1
Main PLL Controller Device-Specific
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
10.5.2
PLL Controller Memory Map . . . . . . . . . . . . . . . . .292
10.5.3
Main PLL Control Registers . . . . . . . . . . . . . . . . . .299
10.5.4
ARM PLL Control Registers . . . . . . . . . . . . . . . . . . .300


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