f =

IN

OutputDivider

FeedbackDivider

(

OUT

PFD

ChargePump

LoopFilter

Feedback

Divider

CE

LVPECL/

LVCMOS/

LVDS

OS[1...0]

OD[2...0]

PR[1...0]

2

2

3

RSTN

Crystal/

LVCMOS

VCO

3.3V

CDCM61001

Output

Driver

LVCMOS

CDCM61001

SCAS869F

– FEBRUARY 2009 – REVISED JUNE 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION, CONTINUED

The CDCM61001 is a high-performance, low phase noise, fully-integrated voltage-controlled oscillator (VCO)

clock synthesizer with one universal output buffer that can be configured to be LVPECL, LVDS, or LVCMOS

compatible. The universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS

bypass output clock is available in an output configuration which can help with crystal loading in order to achieve

an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the 1.75

GHz to 2.05 GHz range.

The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a

low-frequency crystal. The output has an output divider sourced from the VCO core. All device settings are

managed through a control pin structure, which has two pins that control the prescaler and feedback divider,

three pins that control the output divider, two pins that control the output type, and one pin that controls the

output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider)

are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates

a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and divider are turned

off.

datacom applications, refer toTable 2. For other applications, use Equation 1 to calculate the exact crystal

oscillator frequency required for the desired output.

(1)

The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and

prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also

through the use of control pins. Figure 1 shows a high-level block diagram of the CDCM61001.

The device operates in a 3.3-V supply environment and is characterized for operation from

–40°C to +85°C.

Figure 1. CDCM61001 Block Diagram

2

Copyright

© 2009–2011, Texas Instruments Incorporated