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CDCE937PWR Datasheet(PDF) 8 Page - Texas Instruments |
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CDCE937PWR Datasheet(HTML) 8 Page - Texas Instruments |
8 / 39 page 8 CDCE937, CDCEL937 SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016 www.ti.com Product Folder Links: CDCE937 CDCEL937 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VOL SDA low-level output voltage IOL = 3 mA, VDD = 1.7 V 0.2 × VDD V CI SCL/SDA Input capacitance VI = 0 V or VDD 3 10 pF 6.6 Timing Requirements: CLK_IN over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT fCLK LVCMOS clock input frequency PLL bypass mode 0 160 MHz PLL mode 8 160 tr / tf Rise and fall time CLK signal (20% to 80%) 3 ns dutyCLK Duty cycle CLK at VDD/2 40% 60% 6.7 Timing Requirements: SDA/SCL over operating free-air temperature range (unless otherwise noted; see Figure 7) MIN NOM MAX UNIT fSCL SCL clock frequency Standard mode 0 100 kHz Fast mode 0 400 tsu(START) START setup time (SCL high before SDA low) Standard mode 4.7 µs Fast mode 0.6 th(START) START hold time (SCL low after SDA low) Standard mode 4 µs Fast mode 0.6 tw(SCLL) SCL low-pulse duration Standard mode 4.7 µs Fast mode 1.3 tw(SCLH) SCL high-pulse duration Standard mode 4 µs Fast mode 0.6 th(SDA) SDA hold time (SDA valid after SCL low) Standard mode 0 3.45 µs Fast mode 0 0.9 tsu(SDA) SDA setup time Standard mode 250 ns Fast mode 100 tr SCL/SDA input rise time Standard mode 1000 ns Fast mode 300 tf SCL/SDA input fall time 300 ns tsu(STOP) STOP setup time Standard mode 4 µs Fast mode 0.6 tBUS Bus free time between a STOP and START condition Standard mode 4.7 µs Fast mode 1.3 6.8 EEPROM Specification MIN TYP MAX UNIT EEcyc Programming cycles of EEPROM 1000 cycles EEret Data retention 10 years |
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