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LMK61A2-156M25 Datasheet(PDF) 4 Page - Texas Instruments

Part # LMK61A2-156M25
Description  High-Performance Ultra-Low Jitter Oscillator
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

LMK61A2-156M25 Datasheet(HTML) 4 Page - Texas Instruments

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LMK61E0-050M, LMK61E2-100M, LMK61E2-125M, LMK61E2-156M, LMK61E2-312M
LMK61A2-100M, LMK61A2-125M, LMK61A2-156M, LMK61A2-312M, LMK61I2-100M
SNAS676B – OCTOBER 2015 – REVISED MARCH 2017
www.ti.com
Product Folder Links: LMK61E0-050M LMK61E2-100M LMK61E2-125M LMK61E2-156M LMK61E2-312M LMK61A2-
100M LMK61A2-125M LMK61A2-156M LMK61A2-312M LMK61I2-100M
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Copyright © 2015–2017, Texas Instruments Incorporated
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VDD
Device supply voltage
–0.3
3.6
V
VIN
Output voltage for logic inputs
–0.3
VDD + 0.3
V
VOUT
Output voltage for clock outputs
–0.3
VDD + 0.3
V
TJ
Junction temperature
150
°C
TSTG
Storage temperature
–40
125
°C
(1)
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1500
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
Device supply voltage
3.135
3.3
3.465
V
TA
Ambient temperature
–40
25
85
°C
TJ
Junction temperature
LMK61X2
125
°C
LMK61X0
115
°C
tRAMP
VDD power-up ramp time
0.1
100
ms
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2)
The package thermal resistance is calculated on a 4 layer JEDEC board.
(3)
Connected to GND with 3 thermal vias (0.3-mm diameter).
(4)
ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. Please refer to Thermal Considerations
section for more information on ensuring good system reliability and quality.
6.4 Thermal Information
THERMAL METRIC(1)
LMK61XX (2) (3) (4)
UNIT
SIA (QFM)
6 PINS
Airflow (LFM) 0
Airflow (LFM) 200
Airflow (LFM) 400
RθJA
Junction-to-ambient thermal resistance
55.2
46.4
43.7
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
34.6
n/a
n/a
°C/W
RθJB
Junction-to-board thermal resistance
37.7
n/a
n/a
°C/W
ψJT
Junction-to-top characterization parameter
11.3
17.6
22.5
°C/W
ψJB
Junction-to-board characterization parameter
37.7
41.5
40.1
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W


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