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SDA9220-5 Datasheet(PDF) 2 Page - Siemens Semiconductor Group |
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SDA9220-5 Datasheet(HTML) 2 Page - Siemens Semiconductor Group |
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2 / 42 page  SDA 9220-5 Semiconductor Group 118 Circuit Description The MSC III can be divided into the following function blocks (figure 6): – Sync-signal generator – Memory controller – Clock generator – I2C Bus receiver The sync-signal generator uses signals VS and BLN to produce the horizontal and vertical sync signals BLN2, HS2, VS1 and VS2. It supplies the composite sync signal CSY for the 100-Hz teletext, the control signal MUX for implementing a simple frame Featurebox and the frame signal FRM for inserting a colored frame in multi-picture, still-in-picture and picture-in-still modes. Signal CFH is output to prevent the bottom flutter effect in the video cassette recorder mode. In operation without standard conversion (pin-programmable) signals BLN2, VS2 and FRM are switched from double to single line/field frequency. Outputs CSY and HS2 are not required in this case. The memory controller produces the driving signals (RA, RB, WT, RE) and the addresses (SAR, SAC) for the memory devices (TV-SAMs). In addition, it produces the DREQ pulses used for requesting data from the picture processor during operation with reduced pictures. Two refresh operations are performed in the memory for each TV line. The clock generator consists essentially of a PLL which generates the internal and exported system clocks from input clock LL3 or LL1.5 and synchronizes them with the horizontal blanking signal. The MSC can be set to one of the two input frequencies via input LLSEL. For the possible use of the Featurebox as a channel scanner, the PLL incorporates a crystal-controlled reference clock to ensure an undisturbed clock supply for memory output (stills sequence) during channel-switching phases. All modes (except switching off the standard conversion) are set by appropriate programming of the I2C Bus data bytes. When the operating voltage is switched on, all bits of the associated control registers are set to 0. The address of the I2C Bus is set with signal ADR (24H or 26H). |
Similar Part No. - SDA9220-5 |
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Similar Description - SDA9220-5 |
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