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PC97307VUL Datasheet(PDF) 9 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC97307VUL
Description  PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC97307VUL Datasheet(HTML) 9 Page - National Semiconductor (TI)

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Table of Contents
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6.3.7
EPP Data Register 1 (DATA1), Offset 05h ................................................................ 116
6.3.8
EPP Data Register 2 (DATA2), Offset 06h ................................................................ 116
6.3.9
EPP Data Register 3 (DATA3), Offset 07h ................................................................ 117
6.3.10
EPP Mode Transfer Operations ................................................................................ 117
6.3.11
EPP 1.7 and 1.9 Zero Wait State Data Write and Read Operations ......................... 118
6.4
EXTENDED CAPABILITIES PARALLEL PORT (ECP) ........................................................... 119
6.4.1
ECP Modes ............................................................................................................... 119
6.4.2
Software Operation .................................................................................................... 119
6.4.3
Hardware Operation .................................................................................................. 119
6.5
ECP MODE REGISTERS ........................................................................................................ 120
6.5.1
Accessing the ECP Registers .................................................................................... 120
6.5.2
Second Level Offsets ................................................................................................ 120
6.5.3
ECP Data Register (DATAR), Bits 7-5 of ECR = 000 or 001, Offset 000h ................ 121
6.5.4
ECP Address FIFO (AFIFO) Register, Bits 7-5 of ECR = 011, Offset 000h .............. 121
6.5.5
ECP Status Register (DSR), Offset 001h .................................................................. 121
6.5.6
ECP Control Register (DCR), Offset 002h ................................................................ 122
6.5.7
Parallel Port Data FIFO (CFIFO) Register, Bits 7-5 of ECR = 010, Offset 400h ....... 122
6.5.8
ECP Data FIFO (DFIFO) Register, Bits 7-5 of ECR = 011, Offset 400h ................... 122
6.5.9
Test FIFO (TFIFO) Register, Bits 7-5 of ECR = 110, Offset 400h ............................. 123
6.5.10
Configuration Register A (CNFGA), Bits 7-5 of ECR = 111, Offset 400h .................. 123
6.5.11
Configuration Register B (CNFGB), Bits 7-5 of ECR = 111, Offset 401h .................. 123
6.5.12
Extended Control Register (ECR), Offset 402h ......................................................... 124
6.5.13
ECP Extended Index Register (EIR), Offset 403h ..................................................... 125
6.5.14
ECP Extended Data Register (EDR), Offset 404h .................................................... 126
6.5.15
ECP Extended Auxiliary Status Register (EAR), Offset 405h ................................... 126
6.5.16
Control0, Second Level Offset 00h ............................................................................ 126
6.5.17
Control2, Second Level Offset 02h ............................................................................ 126
6.5.18
Control4, Second Level Offset 04h ............................................................................ 127
6.5.19
PP Confg0, Second Level Offset 05h ........................................................................ 127
6.6
DETAILED ECP MODE DESCRIPTIONS ............................................................................... 128
6.6.1
Software Controlled Data Transfer (Modes 000 and 001) ......................................... 128
6.6.2
Automatic Data Transfer (Modes 010 and 011) ........................................................ 128
6.6.3
Automatic Address and Data Transfers (Mode 100) ................................................. 130
6.6.4
FIFO Test Access (Mode 110) .................................................................................. 130
6.6.5
Configuration Registers Access (Mode 111) ............................................................. 130
6.6.6
Interrupt Generation .................................................................................................. 130
6.7
PARALLEL PORT REGISTER BITMAPS ............................................................................... 131
6.7.1
EPP Modes Parallel Port Register Bitmaps ............................................................... 131
6.7.2
ECP Modes Parallel Port Register Bitmaps .............................................................. 132
6.8
PARALLEL PORT PIN/SIGNAL LIST ...................................................................................... 134
7.0
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
7.1
FEATURES .............................................................................................................................. 135
7.2
FUNCTIONAL MODES OVERVIEW ....................................................................................... 135
7.2.1
UART Modes: 16450 or 16550, and Extended .......................................................... 135
7.2.2
Sharp-IR, IrDA SIR Infrared Modes ........................................................................... 135


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