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Si1064-A-GM Datasheet(PDF) 8 Page - Silicon Laboratories |
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Si1064-A-GM Datasheet(HTML) 8 Page - Silicon Laboratories |
8 / 358 page Si106x/108x 8 Rev. 1.0 Figure 8.4. Si108x Flash Program Memory Map ................................................... 124 Figure 12.1. Si106x Flash Program Memory Map ................................................. 151 Figure 12.2. Si108x Flash Program Memory Map ................................................. 152 Figure 13.1. Si106x/108x Power Distribution ........................................................ 161 Figure 14.1. CRC0 Block Diagram ........................................................................ 167 Figure 14.2. Bit Reverse Register ......................................................................... 174 Figure 15.1. DC-DC Converter Block Diagram ...................................................... 175 Figure 15.2. DC-DC Converter Configuration Options .......................................... 178 Figure 17.1. Reset Sources ................................................................................... 185 Figure 17.2. Power-Fail Reset Timing Diagram .................................................... 186 Figure 17.3. Power-Fail Reset Timing Diagram .................................................... 187 Figure 18.1. Clocking Sources Block Diagram ...................................................... 192 Figure 18.2. 25 MHz External Crystal Example ..................................................... 194 Figure 19.1. SmaRTClock Block Diagram ............................................................. 200 Figure 19.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results ......... 209 Figure 20.1. Port I/O Functional Block Diagram .................................................... 217 Figure 20.2. Port I/O Cell Block Diagram .............................................................. 218 Figure 20.3. Crossbar Priority Decoder with No Pins Skipped .............................. 222 Figure 20.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 223 Figure 21.1. SPI Write Command .......................................................................... 239 Figure 21.2. SPI Read Command—Check CTS Value ......................................... 239 Figure 21.3. SPI Read Command—Clock Out Read Data .................................... 240 Figure 21.4. State Machine Diagram ..................................................................... 241 Figure 21.5. POR Timing Diagram ........................................................................ 243 Figure 21.6. Start_TX Commands and Timing ...................................................... 245 Figure 24.1. RX Architecture vs. Data Rate .......................................................... 253 Figure 24.2. +20 dBm TX Power vs. PA_PWR_LVL ............................................. 259 Figure 24.3. +20 dBm TX Power vs. VDD ............................................................. 260 Figure 24.4. +20 dBm TX Power vs. Temp ........................................................... 260 Figure 24.5. Capacitor Bank Frequency Offset Characteristics ............................ 261 Figure 25.1. TX and RX FIFOs .............................................................................. 262 Figure 25.2. Packet Handler Structure .................................................................. 262 Figure 27.1. RX and TX LDC Sequences .............................................................. 265 Figure 27.2. Low Duty Cycle Mode for RX ............................................................ 265 Figure 28.1. SMBus Block Diagram ...................................................................... 267 Figure 28.2. Typical SMBus Configuration ............................................................ 268 Figure 28.3. SMBus Transaction ........................................................................... 269 Figure 28.4. Typical SMBus SCL Generation ........................................................ 271 Figure 28.5. Typical Master Write Sequence ........................................................ 282 Figure 28.6. Typical Master Read Sequence ........................................................ 283 Figure 28.7. Typical Slave Write Sequence .......................................................... 284 Figure 28.8. Typical Slave Read Sequence .......................................................... 285 Figure 29.1. UART0 Block Diagram ...................................................................... 290 Figure 29.2. UART0 Baud Rate Logic ................................................................... 291 Figure 29.3. UART Interconnect Diagram ............................................................. 292 |
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