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EFR32MG1P232F256GM48-B0 Datasheet(PDF) 8 Page - Silicon Laboratories |
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EFR32MG1P232F256GM48-B0 Datasheet(HTML) 8 Page - Silicon Laboratories |
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8 / 80 page  3.3.13 True Random Number Generator The Frame Controller (FRC) implements a true random number generator that extracts noise from the RF receive chain. Data can be read from a register 32 bits at a time, or larger blocks of random data can be written directly to RAM. Output from the random number generator can be used either directly or as a seed or entropy source for software based random num- ber generator algorithms such as Fortuna. 3.3.14 System Processor The ARM Cortex-M processor subsystem integrates the following features and tasks in the system: • 32-bit ARM Cortex-M RISC processor achieving 1.25 Dhrystone MIPS/MHz • Memory Protection Unit (MPU) supporting up to 8 memory segments • Up to 256 kB flash program memory • Up to 32 kB RAM data memory • Advanced and flexible protocol support, in cooperation with the Frame Controller • Configuration and event handling of all modules • 2-pin Serial-Wire debug interface, which can be disabled The Cortex-M4 is equipped with DSP instruction support and a floating-point unit (FPU). 3.3.15 Memory System Controller (MSC) The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in en- ergy modes EM0 Active/EM1 Sleep. 3.3.16 Linked Direct Memory Access Controller (LDMA) The Linked Direct Memory Access (LDMA) controller features 8 channels capable of performing memory operations independently of software. This reduces both energy consumption and software workload. 3.3.17 Integrated Voltage Regulators The EFR32MG1X232 generates internal supply voltages from integrated regulators. This means that only a single external supply volt- age is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator, further detailed in section 3.3.37 Integrated DC-DC Converter (DC-DC), can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capacitor. 3.3.18 Reset Management Unit (RMU) The RMU is responsible for handling reset of the EFR32MG1X232. A wide range of reset sources are available, including several pow- er supply monitors, pin reset, software controlled reset, core lockup reset and watchdog reset. 3.3.19 Energy Management Unit (EMU) The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and features are available. The EMU can also be used to turn off the power to unused RAM blocks. The EMU also contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple supply voltages. It has 4 channels which can be programmed individually by the user to determine if a sensed supply has fallen below a chosen threshold. 3.3.20 Clock Management Unit (CMU) The Clock Management Unit controls oscillators and clocks in the EFR32MG1X232. Individual enabling and disabling of clocks to all peripheral modules is perfomed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused periph- erals and oscillators. EFR32MG1X232 Data Sheet System Overview silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.71 | 7 |
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