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PC87311 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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PC87311 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
11 / 78 page 10 Pin Description (Continued) Symbol Pin IO Function SOUT12 73 65 O Serial Output This output sends composite serial data to the communications link (peripheral device MODEM or data set) The SOUT signal is set to a marking state (logic 1) after a Master Reset operation (See BOUT and CFG0 – 4 for further information on these pins) STB 95 O Data Strobe This output indicates to the printer that valid data is available at the printer port This pin will be in a TRI-STATE condition 10 ns after a zero is loaded into the corresponding Control Register bit The system should pull this pin high using a 47 kX resistor STEP 40 O Step This output signal issues pulses to the disk drive at a software programmable rate to move the head during a seek operation TC 6 I Terminal Count Control signal from the DMA controller to indicate the termination of a DMA transfer TC is accepted only when DACK is active TC is active high in PC-AT and Model 30 modes and active low in PS2 mode TRK0 37 I Track 0 This input indicates to the controller that the head of the selected floppy disk drive is at track zero VDDA 33 Analog Supply This pin is the 5V supply for the analog data separator VDDBC 50 99 Digital Supply This is the 5V supply voltage for the digital circuitry VSSA 31 Analog Ground This is the analog ground for the data separator VSSB-E 42 9 Digital Ground This is the ground for the digital circuitry 90 61 WR 18 I Write Active low input to signal a write from the microprocessor to the controller WDATA 39 O Write Data This output is the write precompensated serial data that is written to the selected floppy disk drive Precompensation is software selectable WGATE 38 O Write Gate This output signal enables the write circuitry of the selected disk drive WGATE has been designed to prevent glitches during power up and power down This prevents writing to the disk when power is cycled WP 36 I Write Protect This input indicates that the disk in the selected drive is write protected X1OSC 7 I Crystal1Clock One side of an external 24 MHz crystal is attached here If a crystal is not used a TTL or CMOS compatible clock is connected to this pin X2 8 O Crystal2 One side of an external 24 MHz crystal is attached here This pin is left unconnected if an external clock is used XTSEL 63 I XT Select When this pin is high during reset the chip will operate in the XT mode When this pin is low during reset the chip will operate in the AT mode An internal pull-down resistor of 40 kX is on this pin Usea10kX resistor to pull this pin to the required level during reset There are five differences between AT and XT mode One concerns hard disk operation and the other four concern UART operation In AT mode the IDE hard drive chip selects (HCS0 HCS1) will be active for addresses 1F0 – 7H and 3F6 7H respectively In XT mode the IDE chip select HCS0 responds to addresses 320 – 3H and HCS1 is inactive The differences in UART operation are the function of LSR bit (see Section 65 bit 6) the modem control outputs during loop back mode (see Section 68 bit 4) the Scratch Pad Register (see Section 610) and the availability of edge (XT) or level (AT) sensitive UART interrupts Note XTSEL is an option for the PC87311A only 11 |
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Similar Description - PC87311 |
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