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DRV870XD-Q1 Datasheet(PDF) 3 Page - Texas Instruments |
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DRV870XD-Q1 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 66 page  1 GND 24 RSVD 2 IN1 23 SP 3 IN2 22 SN 4 SDO 21 SP 5 nSCS 20 GL 6 SDI 19 SH 7 SCLK 18 GH 8 nSLEEP 17 GND Not to scale Thermal Pad 1 GND 24 RSVD 2 IN1 23 SP 3 IN2 22 SN 4 GND 21 SP 5 IDRIVE 20 GL 6 VDS 19 SH 7 GND 18 GH 8 nSLEEP 17 GND Not to scale Thermal Pad 3 DRV8702D-Q1, DRV8703D-Q1 www.ti.com SLVSDX8 – MARCH 2017 Product Folder Links: DRV8702D-Q1 DRV8703D-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 5 Pin Configuration and Functions DRV8702D-Q1 RHB Package With Wettable Flanks 32-Pin VQFN Top View DRV8703D-Q1 RHB Package With Wettable Flanks 32-Pin VQFN Top View (1) I = input, O = output, PWR = power, NC = no connect, OD = open-drain output Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. DRV8702D-Q1 DRV8703D-Q1 AVDD 14 14 PWR Analog regulator. This pin is the 5-V analog supply regulator. Bypass this pin to ground with a 6.3-V, 1-µF ceramic capacitor. CPH 30 30 PWR Charge-pump switching node. Connect a 0.1-µF X7R capacitor rated for the supply voltage (VM) between the CPH and CPL pins. CPL 31 31 PWR Charge-pump switching node. Connect a 0.1-µF X7R capacitor rated for the supply voltage (VM) between the CPH and CPL pins. DVDD 12 12 PWR Logic regulator. This pin is the regulator for the 3.3-V logic supply. Bypass this pin to ground with a 6.3-V, 1-µF ceramic capacitor. GH 18 18 O High-side gate. Connect this pin to the high-side FET gate. GL 20 20 O Low-side gate. Connect this pin to the low-side FET gate. GND 1 1 PWR Device ground. Connect this pin to the system ground. GND 13 13 PWR Device ground. Connect this pin to the system ground. GND 17 17 PWR Device ground. Connect this pin to the system ground. GND 25 25 PWR Device ground. Connect this pin to the system ground. GND 4 — PWR Device ground. Connect this pin to the system ground. GND 7 — PWR Device ground. Connect this pin to the system ground. GND 9 — PWR Device ground. Connect this pin to the system ground. IDRIVE 5 — I Current setting pin for the gate drive. The resistor value or voltage forced on this pin sets the gate-drive current. For more information see the IDRIVE Configuration section. IN1 2 2 I Input control pins. The logic of this pin is dependent on the MODE pin. IN2 3 3 I Input control pins. The logic of this pin is dependent on the MODE pin. |
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