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PC87360 Datasheet(PDF) 9 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC87360
Description  128-Pin LPC SuperI/O with Protection and Extensive GPIO Support
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87360 Datasheet(HTML) 9 Page - National Semiconductor (TI)

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Table of Contents (Continued)
9
www.national.com
5.4
FAN SPEED MONITOR BITMAP ............................................................................................ 114
6.0
General-Purpose Input/Output (GPIO) Port
6.1
OVERVIEW ............................................................................................................................. 115
6.2
BASIC FUNCTIONALITY ........................................................................................................ 116
6.2.1
Configuration Options ................................................................................................ 116
6.2.2
Operation ................................................................................................................... 116
6.3
EVENT HANDLING AND SYSTEM NOTIFICATION .............................................................. 117
6.3.1
Event Configuration ................................................................................................... 117
Event Type and Polarity ............................................................................................ 117
Event Debounce Enable ............................................................................................ 117
6.3.2
System Notification .................................................................................................... 117
6.4
GPIO PORT REGISTERS ....................................................................................................... 118
6.4.1
GPIO Pin Configuration (GPCFG) Register .............................................................. 119
6.4.2
GPIO Pin Event Routing (GPEVR) Register ............................................................. 120
6.4.3
GPIO Port Runtime Register Map ............................................................................. 120
6.4.4
GPIO Data Out Register (GPDO) .............................................................................. 121
6.4.5
GPIO Data In Register (GPDI) .................................................................................. 121
6.4.6
GPIO Event Enable Register (GPEVEN) .................................................................. 122
6.4.7
GPIO Event Status Register (GPEVST) .................................................................... 122
7.0
WATCHDOG Timer (WDT)
7.1
OVERVIEW ............................................................................................................................. 123
7.2
FUNCTIONAL DESCRIPTION ................................................................................................ 123
7.3
WATCHDOG TIMER REGISTERS ......................................................................................... 124
7.3.1
WATCHDOG Timer Register Map ............................................................................. 124
7.3.2
WATCHDOG Timeout Register (WDTO) .................................................................. 124
7.3.3
WATCHDOG Mask Register (WDMSK) .................................................................... 125
7.3.4
WATCHDOG Status Register (WDST) ...................................................................... 126
7.4
WATCHDOG TIMER REGISTER BITMAP ............................................................................. 126
8.0
ACCESS.bus Interface (ACB)
8.1
OVERVIEW ............................................................................................................................. 127
8.2
FUNCTIONAL DESCRIPTION ................................................................................................ 127
8.2.1
Data Transactions ..................................................................................................... 127
8.2.2
Start and Stop Conditions .......................................................................................... 127
8.2.3
Acknowledge (ACK) Cycle ........................................................................................ 128
8.2.4
Acknowledge after Every Byte Rule .......................................................................... 129
8.2.5
Addressing Transfer Formats .................................................................................... 129
8.2.6
Arbitration on the Bus ................................................................................................ 129
8.2.7
Master Mode .............................................................................................................. 130
Requesting Bus Mastership ....................................................................................... 130
Sending the Address Byte ......................................................................................... 130
Master Transmit ......................................................................................................... 130
Master Receive .......................................................................................................... 131
Master Stop ............................................................................................................... 131


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