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W25Q256JVFIQ Datasheet(PDF) 10 Page - Winbond |
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W25Q256JVFIQ Datasheet(HTML) 10 Page - Winbond |
10 / 92 page W25Q256JV - 9 - 4. PIN DESCRIPTIONS 4.1 Chip Select (/CS) The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure 58). If needed a pull-up resistor on the /CS pin can be used to accomplish this. 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) The W25Q256JV supports Standard SPI, Dual SPI and Quad SPI operation. All 8-bit instructions are shifted into the device through DI (IO0) pin, address and data are shifted in and out of the device through either DI & DO pins for Standard SPI instructions, IO0 & IO1 pins for Dual SPI instructions, or IO0-IO3 pins for Quad SPI instructions. 4.3 Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Operations") 4.4 Reset (/RESET)(1) A dedicated hardware /RESET pin is available on SOIC- 16 and TFBGA packages. When it’s driven low for a minimum period of ~1µS, this device will terminate any external or internal operations and return to its power-on state. Note: Hardware /RESET pin is available on SOIC-16 or TFBGA; please contact Winbond for this package. |
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