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TLV320AIC3104IRHBT Datasheet(PDF) 6 Page - Texas Instruments |
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TLV320AIC3104IRHBT Datasheet(HTML) 6 Page - Texas Instruments |
6 / 97 page 6 TLV320AIC3104 SLAS510F – FEBRUARY 2007 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: TLV320AIC3104 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22- C101(2) ±1500 (1) Analog voltage values are with respect to AVSS1, AVSS2, DRVSS; digital voltage values are with respect to DVSS. 8.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD, DRVDD1/2(1) Analog supply voltage 2.7 3.3 3.6 V DVDD(1) Digital core supply voltage 1.525 1.8 1.95 V IOVDD(1) Digital I/O supply voltage 1.1 1.8 3.6 V VI Analog full-scale 0-dB input voltage (DRVDD1 = 3.3 V) 0.707 VRMS Stereo line output load resistance 10 k Ω Stereo headphone output load resistance 16 Ω Digital output load capacitance 10 pF TA Operating free-air temperature –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, . 8.4 Thermal Information THERMAL METRIC(1) TLV320AIC3104 UNIT RHB 32 PINS RθJA Junction-to-ambient thermal resistance 31.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 22.3 RθJB Junction-to-board thermal resistance 5.9 ψJT Junction-to-top characterization parameter 0.3 ψJB Junction-to-board characterization parameter 5.9 RθJC(bot) Junction-to-case (bottom) thermal resistance 1.2 (1) It is required to limit the power dissipation within the package to 500 mW in all cases, including temperatures below 25°C. This data is based on using a JEDEC standard four-layer 3-in. × 3-in. (7.62-mm × 7.62-mm) PCB with 2-oz. (0.071-mm thick) trace and copper pad that is soldered directly to the device. 8.5 System Thermal Characteristics (1) Power Rating at 25°C, mW Power Rating, mW Derating Factor, °C/W High-K Board 500 500 at 80°C 48 Low-K Board 500 500 at 30°C 148 |
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